Search Results - "Balachandran, H."

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  1. 1

    K longest paths per gate (KLPG) test generation for scan-based sequential circuits by Qiu, W., Jing Wang, Walker, D.M.H., Reddy, D., Xiang Lu, Zhuo Li, Weiping Shi, Balachandran, H.

    “…To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are…”
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    Conference Proceeding
  2. 2

    Microalbuminuria in patients with essential hypertension and its relationship to target organ damage : an Indian experience by Sujathan, P., Pillai, H. Balachandran, Pappachan, Jospeh M., Misiriya, K. J. Raihanathul, Jayaprakash, K., Ramakrishna, C. D., Hitha, B.

    “…Persistent micro albuminuria (MA) is the earliest indicator of chronic kidney disease (CKD) in patients with diabetes mellitus and hypertension. Patients with…”
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    Journal Article
  3. 3

    Logic mapping on a microprocessor by Kinra, A., Balachandran, H., Thomas, R., Carulli, J.

    “…Improving debug techniques for logic failures is a constant imperative. This paper describes the results of implementing a logic mapping methodology that…”
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    Conference Proceeding Journal Article
  4. 4

    REDO-random excitation and deterministic observation-first commercial experiment by Grimaila, M.R., Sooryong Lee, Dworak, J., Butler, K.M., Stewart, B., Balachandran, H., Houchins, B., Mathur, V., Jaehong Park, Wang, L.-C., Mercer, M.R.

    “…For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective…”
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    Conference Proceeding
  5. 5

    Facilitating rapid first silicon debug by Balachandran, H., Butler, K.M., Simpson, N.

    “…Semiconductor manufacturers aim to deliver products to market within a short span of time in order to gain market share. There are several facets of…”
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    Conference Proceeding
  6. 6

    Computer-aided fault to defect mapping (CAFDM) for defect diagnosis by Stanojevic, Z., Balachandran, H., Walker, D.M.H., Lakbani, F., Jandhyala, S., Saxena, J., Butler, K.M.

    “…Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this…”
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    Conference Proceeding
  7. 7

    Improvement of SRAM-based failure analysis using calibrated Iddq testing by Balachandran, H., Walker, D.M.H.

    “…This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap…”
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    Conference Proceeding
  8. 8

    Defect localization using physical design and electrical test information by Stanojevic, Z., Balachandran, H., Walker, D.M.H., Lakhani, F., Jandhyala, S.

    “…In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach…”
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    Conference Proceeding
  9. 9

    On applying non-classical defect models to automated diagnosis by Saxena, J., Butler, K.M., Balachandran, H., Lavo, D.B., Chess, B., Larrabee, T., Ferguson, F.J.

    “…Automated fault diagnosis based on the stuck-at fault model is not always effective. This paper presents practical experiences in applying a bridging fault…”
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    Conference Proceeding
  10. 10

    Clustering based techniques for I/sub DDQ/ testing by Jandhyala, S., Balachandran, H., Jayasumana, A.P.

    “…A new technique for evaluating I/sub DDQ/ data using a clustering based approach is presented. While prevailing I/sub DDQ/ test techniques rely on a fixed…”
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    Conference Proceeding
  11. 11

    Clustering based evaluation of I/sub DDQ/ measurements: applications in testing and classification of ICs by Jandhyala, S., Balachandran, H., Sengupta, M., Jayasumana, A.P.

    “…Effectiveness of the clustering based approach in detecting devices with abnormal I/sub DDQ/ values is evaluated using data from the SEMATECH test methods…”
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    Conference Proceeding
  12. 12

    Correlation of logical failures to a suspect process step by Balachandran, H., Parker, J., Shupp, D., Butler, S., Butler, K.M., Force, C., Smith, J.

    “…Traditional yield enhancement efforts have long relied on memory bitmapping techniques. With the industry marching toward system-on-a-chip technology, the…”
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    Conference Proceeding
  13. 13

    Expediting ramp-to-volume production by Balachandran, H., Parker, J., Gammie, G., Olson, J., Force, C., Butler, K.M., Jandhyala, S.

    “…High levels of integration have complicated the entire IC manufacturing process. Crucial steps such as ramp to volume production and yield improvement…”
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    Conference Proceeding
  14. 14

    Clustering based identification of faulty ICs using I/sub DDQ/ tests by Jandhyala, S., Balachandran, H., Menon, S., Jayasumana, A.

    “…Technological advances in design and process have led to questions being raised about the applicability of I/sub DDQ/ testing. The main concern is the…”
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    Conference Proceeding