Search Results - "Balachandran, H."
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1
K longest paths per gate (KLPG) test generation for scan-based sequential circuits
Published in 2004 International Conferce on Test (2004)“…To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are…”
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Conference Proceeding -
2
Microalbuminuria in patients with essential hypertension and its relationship to target organ damage : an Indian experience
Published in Saudi journal of kidney diseases and transplantation (01-05-2008)“…Persistent micro albuminuria (MA) is the earliest indicator of chronic kidney disease (CKD) in patients with diabetes mellitus and hypertension. Patients with…”
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Journal Article -
3
Logic mapping on a microprocessor
Published in Proceedings - International Test Conference (2000)“…Improving debug techniques for logic failures is a constant imperative. This paper describes the results of implementing a logic mapping methodology that…”
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Conference Proceeding Journal Article -
4
REDO-random excitation and deterministic observation-first commercial experiment
Published in Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) (1999)“…For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective…”
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Conference Proceeding -
5
Facilitating rapid first silicon debug
Published in Proceedings - International Test Conference (2002)“…Semiconductor manufacturers aim to deliver products to market within a short span of time in order to gain market share. There are several facets of…”
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Conference Proceeding -
6
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis
Published in Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) (2000)“…Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this…”
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Conference Proceeding -
7
Improvement of SRAM-based failure analysis using calibrated Iddq testing
Published in Proceedings of 14th VLSI Test Symposium (1996)“…This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap…”
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Conference Proceeding -
8
Defect localization using physical design and electrical test information
Published in 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072) (2000)“…In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach…”
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Conference Proceeding -
9
On applying non-classical defect models to automated diagnosis
Published in Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) (1998)“…Automated fault diagnosis based on the stuck-at fault model is not always effective. This paper presents practical experiences in applying a bridging fault…”
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Conference Proceeding -
10
Clustering based techniques for I/sub DDQ/ testing
Published in International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)“…A new technique for evaluating I/sub DDQ/ data using a clustering based approach is presented. While prevailing I/sub DDQ/ test techniques rely on a fixed…”
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Conference Proceeding -
11
Clustering based evaluation of I/sub DDQ/ measurements: applications in testing and classification of ICs
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)“…Effectiveness of the clustering based approach in detecting devices with abnormal I/sub DDQ/ values is evaluated using data from the SEMATECH test methods…”
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Conference Proceeding -
12
Correlation of logical failures to a suspect process step
Published in International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)“…Traditional yield enhancement efforts have long relied on memory bitmapping techniques. With the industry marching toward system-on-a-chip technology, the…”
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Conference Proceeding -
13
Expediting ramp-to-volume production
Published in International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)“…High levels of integration have complicated the entire IC manufacturing process. Crucial steps such as ramp to volume production and yield improvement…”
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Conference Proceeding -
14
Clustering based identification of faulty ICs using I/sub DDQ/ tests
Published in Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) (1998)“…Technological advances in design and process have led to questions being raised about the applicability of I/sub DDQ/ testing. The main concern is the…”
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Conference Proceeding