Methodology Verification of Hierarchically Described VLSI Circuits

Methodology Verification of Hierarchically Described VLSI Circuits

The standard approach to master the complexity of designing VLSI systems is to adopt a set of rules that, when respected, are conducive to correct implementations. Any such collection of rules can be called a design methodology. Most of the effort in computer-aided VLSI methodology verification has...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems Vol. 6; no. 1; pp. 111 - 115
Main Authors: Bain, I.L., Glasser, L.A.
Format: Journal Article
Language:English
Published: New York, NY IEEE 01-01-1987
Institute of Electrical and Electronics Engineers
Subjects:
Applied sciences
Circuit topology
Clocks
Computer aided instruction
Design methodology
Electronics
Exact sciences and technology
High level languages
Integrated circuits
MOS devices
Process design
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
Very large scale integration
Wiring
Operator
MOS technology
VLSI circuit
Methodology
Computer program
Interconnection
Integrated circuit
Digital circuit
Verification
Computer aided design
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Summary:The standard approach to master the complexity of designing VLSI systems is to adopt a set of rules that, when respected, are conducive to correct implementations. Any such collection of rules can be called a design methodology. Most of the effort in computer-aided VLSI methodology verification has been traditionally concentrated on geometrical DRC. This paper describes a program that checks circuit conformity to other kinds of rules. This is done at the transistor level, and most of the rules are user-selected. Two related issues are also discussed: the description of digital MOS circuits using wiring operators; and the formal description of methodologies by the designer.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.1987.1270253