13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

With the emergence of large-language models (LLM) and generative AI, which require an enormous amount of model parameters, the required memory bandwidth and capacity for high-end systems is on an unprecedented increase. To meet this need, we present an extended version of the high-bandwidth memory-3...

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Bibliographic Details
Published in:	2024 IEEE International Solid-State Circuits Conference (ISSCC) Vol. 67; pp. 238 - 240
Main Authors:	Lee, Jinhyung, Cho, Kyungjun, Lee, Chang Kwon, Lee, Yeonho, Park, Jae-Hyung, Oh, Su-Hyun, Ju, Yucheon, Jeong, Chunseok, Cho, Ho Sung, Lee, Jaeseung, Yun, Tae-Sik, Cho, Jin Hee, Oh, Sangmuk, Moon, Junil, Park, Young-Jun, Choi, Hong-Seok, Kim, In-Keun, Yang, Seung Min, Kim, Sun-Yeol, Jang, Jaemin, Kim, Jinwook, Lee, Seong-Hee, Jeon, Younghyun, Park, Juhyung, Kim, Tae-Kyun, Ka, Dongyoon, Oh, Sanghoon, Kim, Jinse, Jeon, Junyeol, Kim, Seonhong, Kim, Kyeong Tae, Kim, Taeho, Yang, Hyeonjin, Yang, Dongju, Lee, Minseop, Song, Heewoong, Jang, Dongwook, Shin, Junghyun, Kim, Hyunsik, Baek, Changki, Jeong, Hajun, Yoon, Jongchan, Lim, Seung-Kyun, Lee, Kyo Yun, Koo, Young Jun, Park, Myeong-Jae, Cho, Joohwan, Kim, Jonghwan
Format:	Conference Proceeding
Language:	English
Published:	IEEE 18-02-2024
Subjects:	Bandwidth Generative AI Memory management Random access memory Reliability engineering Solid state circuits Voltage
Online Access:	Get full text
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Summary:	With the emergence of large-language models (LLM) and generative AI, which require an enormous amount of model parameters, the required memory bandwidth and capacity for high-end systems is on an unprecedented increase. To meet this need, we present an extended version of the high-bandwidth memory-3 (HBM3 DRAM), HBM3E, which achieves a 1280GB/s bandwidth with a cube density of 48GB. New design schemes and features, such as all-around power-through-silicon via (TSV), a 6-phase read-data-strobe (RDQS) scheme, a byte-mapping swap scheme, and a voltage-drift compensator for write data strobe (WDQS), are implemented to achieve extended bandwidth and capacity with enhanced reliability. The overall architecture and specifications, such as bump map footprint, the number of channel and I/Os, and the operation voltage, are identical to the latest HBM3 [1, 2]; therefore, backward compatibility is provided, avoiding system modification.
ISSN:	2376-8606
DOI:	10.1109/ISSCC49657.2024.10454440