Search Results - "Badaroglu, M"

Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics by Firouzi, Farshad, Rahmani, Amir M., Mankodiya, K., Badaroglu, M., Merrett, G.V., Wong, P., Farahani, Bahar

“…The technology and healthcare industries have been deeply intertwined for quite some time. New opportunities, however, are now arising as a result of…”
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Metrology for the next generation of semiconductor devices by Orji, N. G., Badaroglu, M., Barnes, B. M., Beitia, C., Bunday, B. D., Celano, U., Kline, R. J., Neisser, M., Obeng, Y., Vladar, A. E.

“…The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate…”
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Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation by Ryckaert, J., Desset, C., Fort, A., Badaroglu, M., De Heyn, V., Wambacq, P., Van der Plas, G., Donnay, S., Van Poucke, B., Gyselinckx, B.

“…The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget of the autonomous sensor…”
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Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal by Mertens, H., Ritzenthaler, R., Arimura, H., Franco, J., Sebaai, F., Hikavyy, A., Pawlak, B. J., Machkaoutsan, V., Devriendt, K., Tsvetanova, D., Milenin, A. P., Witters, L., Dangol, A., Vancoille, E., Bender, H., Badaroglu, M., Holsteyns, F., Barla, K., Mocuta, D., Horiguchi, N., Thean, A. V.-Y

“…We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We…”
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A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication by Ryckaert, J., Verhelst, M., Badaroglu, M., D'Amico, S., De Heyn, V., Desset, C., Nuzzo, P., Van Poucke, B., Wambacq, P., Baschirotto, A., Dehaene, W., Van der Plas, G.

“…A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature…”
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Holistic technology optimization and key enablers for 7nm mobile SoC by Song, S. C., Xu, J., Mojumder, N. N., Rim, K., Yang, D., Bao, J., Zhu, J., Wang, J., Badaroglu, M., Machkaoutsan, V., Narayanasetti, P., Bucki, B., Fischer, J., Yeap, Geoffrey

“…We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly…”
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Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification by van Heijningen, M., Badaroglu, M., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling…”
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Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate by Soens, C., Van der Plas, G., Badaroglu, M., Wambacq, P., Donnay, S., Rolain, Y., Kuijk, M.

“…Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations…”
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Evolution of substrate noise generation mechanisms with CMOS technology scaling by Badaroglu, M., Wambacq, P., Van der Plas, G., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS…”
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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits by Badaroglu, M., van Heijningen, M., Gravot, V., Compiet, J., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured…”
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Digital ground bounce reduction by supply current shaping and clock frequency Modulation by Badaroglu, M., Wambacq, P., Van der Plas, G., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp…”
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Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies by Badaroglu, M., Donnay, S., De Man, H.J., Zinzius, Y.A., Gielen, G.G.E., Sansen, W., Fonden, T., Signell, S.

“…Substrate noise is a major obstacle for mixed-signal integration. While the power consumption scales linearly with the clock frequency, substrate noise does…”
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SWAN: high-level simulation methodology for digital substrate noise generation by Badaroglu, M., Van der Plas, G., Wambacq, P., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore…”
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Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate by Badaroglu, M., Van der Plas, G., Wambacq, P., Balasubramanian, L., Tiri, K., Verbauwhede, I., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance…”
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Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding by Badaroglu, M., Tiri, K., Van der Plas, G., Wambacq, P., Verbauwhede, I., Donnay, S., Gielen, G.G.E., De Man, H.J.

“…In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge; therefore, they generate a lot of…”
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High-level simulation of substrate noise generation including power supply noise coupling by van Heijningen, Marc, Badaroglu, Mustafa, Donnay, Stéphane, Engels, Marc, Bolsens, Ivo

“…Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance…”
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Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification by Van Heijningen, M., Badaroglu, M., Donnay, S., De Man, H., Gielen, G., Engels, M., Bolsens, I.

“…More and more system-on-chip designs require the integration of analog circuits on large digital chips and therefore suffer from substrate noise coupling. To…”
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Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires by Bardon, M. Garcia, Sherazi, Y., Schuddinck, P., Jang, D., Yakimets, D., Debacker, P., Baert, R., Mertens, H., Badaroglu, M., Mocuta, A., Horiguchi, N., Mocuta, D., Raghavan, P., Ryckaert, J., Spessot, A., Verkest, D., Steegen, A.

“…By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without…”
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Holistic technology optimization and key enablers for 7nm mobile SoC by Song, S. C., Xu, J., Mojumder, N. N., Rim, K., Yang, D., Bao, J., Zhu, J., Wang, J., Badaroglu, M., Machkaoutsan, V., Narayanasetti, P., Bucki, B., Fischer, J., Yeap, Geoffrey

“…We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly…”
Get full text

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects by Van der Plas, G., Badaroglu, M., Vandersteen, G., Dobrovolny, P., Wambacq, P., Donnay, S., Gielen, G., De Man, H.

“…Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate…”
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