Search Results - "Baas, Bevan M"

Parallel AES Encryption Engines for Many-Core Processor Arrays by Bin Liu, Baas, B. M.

“…By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an Advanced Encryption Standard (AES) cipher with…”
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Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays by Wu, Shifu, Baas, Bevan M.

“…This brief presents two software Display Stream Compression (DSC) video decoder designs for many-core processor arrays. The first design exploits fine-grained…”
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KiloCore: A 32-nm 1000-Processor Computational Array by Bohnenstiehl, Brent, Stillmaker, Aaron, Pimentel, Jon J., Andreas, Timothy, Bin Liu, Tran, Anh T., Adeagbo, Emmanuel, Baas, Bevan M.

“…A processor array containing 1000 independent processors and 12 memory modules was fabricated in 32-nm partially depleted silicon on insulator CMOS. The…”
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A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders by Mohsenin, Tinoosh, Truong, Dean N, Baas, Bevan M

“…A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout…”
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A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors by Zhiyi Yu, Baas, Bevan M

“…A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports…”
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Achieving High-Performance On-Chip Networks With Shared-Buffer Routers by Tran, Anh T., Baas, Bevan M.

“…On-chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs on output physical…”
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Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs by Pimentel, Jon J., Bohnenstiehl, Brent, Baas, Bevan M.

“…Hybrid floating-point (FP) implementations improve software FP performance without incurring the area overhead of full hardware FP units. The proposed…”
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Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks by Zhibin Xiao, Baas, Bevan M.

“…We propose two eight-neighbor, two five-nearest-neighbor, and three six-nearest-neighbor interconnection topologies for many-core processor arrays-three of…”
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A 167-Processor Computational Platform in 65 nm CMOS by Truong, D.N., Cheng, W.H., Mohsenin, T., Zhiyi Yu, Jacobson, A.T., Landge, G., Meeuwsen, M.J., Watnik, C., Tran, A.T., Zhibin Xiao, Work, E.W., Webb, J.W., Mejia, P.V., Baas, B.M.

“…A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock…”
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A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System by Zhibin Xiao, Baas, B. M.

“…This paper presents a baseline residual encoder for H.264/AVC on a programmable fine-grained many-core processing array that utilizes no application-specific…”
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A low-power, high-performance, 1024-point FFT processor by Baas, B.M.

“…This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a…”
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Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms by Foroozannejad, Mohammad H., Hashemi, Matin, Mahini, Alireza, Baas, Bevan M., Ghiasi, Soheil

“…We study the problem of mapping concurrent tasks of an application to cores of a chip multiprocessor that utilize circuit-switched interconnect and global…”
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AsAP: An Asynchronous Array of Simple Processors by Zhiyi Yu, Meeuwsen, M.J., Apperson, R.W., Sattari, O., Lai, M., Webb, J.W., Work, E.W., Truong, D., Mohsenin, T., Baas, B.M.

“…An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor…”
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High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors by Zhiyi Yu, Baas, B.M.

“…Chip multiprocessors with globally asynchronous locally synchronous (GALS) clocking styles are promising candidates for processing computationally-intensive…”
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A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders by Mohsenin, Tinoosh, Baas, Bevan M.

“…A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The…”
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Area efficient backprojection computation with reduced floating-point word width for SAR image formation by Pimentel, Jon J., Stillmaker, Aaron, Bohnenstiehl, Brent, Baas, Bevan M.

“…The widths of data words in digital processors have a direct impact on area in application-specific ICs (ASICs) and FPGAs. Circuit area impacts energy…”
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A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains by Apperson, R.W., Zhiyi Yu, Meeuwsen, M.J., Mohsenin, T., Baas, B.M.

“…A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in…”
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Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling by Bin Liu, Foroozannejad, Mohammad H., Ghiasi, Soheil, Baas, Bevan M.

“…To address the well-known "power wall" issue, many-core processors with dynamic voltage and frequency scaling (DVFS) are widely investigated. To further…”
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Hybrid floating-point modules with low area overhead on a fine-grained processing core by Pimentel, Jon J., Baas, Bevan M.

“…This paper proposes Hybrid Floating-Point Modules (HFPMs) as a method to improve software floating-point (FP) throughput without incurring the area overhead of…”
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Scalable hardware-based power management for many-core systems by Bin Liu, Bohnenstiehl, Brent, Baas, Bevan M.

“…Due to high levels integration, the design of many-core systems becomes increasingly challenging. Runtime dynamic voltage and frequency scaling (DVFS) is an…”
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