Search Results - "Assous, Myriam"

Warpage control of silicon interposer for 2.5D package application by Murayama, Kei, Aizawa, Mitsuhiro, Hara, Koji, Sunohara, Masahiro, Miyairi, Ken, Mori, Kenichi, Charbonnier, Jean, Assous, Myriam, Bally, Jean-Philippe, Simon, Gilles, Higashi, Mitsutoshi

“…In order to achieve high speed transmission and large volume data processing, large size silicon-interposer has been required. Warpage caused by the CTE…”
Get full text

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems by Thonnart, Yvain, Bernabe, Stephane, Charbonnier, Jean, Bernard, Christian, Coriat, David, Fuguet, Cesar, Tissier, Pierre, Charbonnier, Benoit, Malhouitre, Stephane, Saint-Patrice, Damien, Assous, Myriam, Narayan, Aditya, Coskun, Ayse, Dutoit, D., Vivet, P.

“…Silicon photonics technology is now gaining maturity with increasing levels of design complexity from devices to large photonic integrated circuits. Close…”
Get full text

Specificities of linear Si QD arrays integration and characterization by Niebojewski, H., Bertrand, B., Nowak, E., Bedecarrats, T., Paz, B. Cardoso, Contamin, L., Mortemousque, P.A., Labracherie, V., Brevard, L., Sahin, H., Charbonnier, J., Thomas, C., Assous, M., Casse, M., Urdampilleta, M., Niquet, Y.-M., Perruchot, F., Gaillard, F., De Franceschi, S., Meunier, T., Vinet, M.

“…The low temperature operation of quantum computing devices implies developing characterization protocols, from extensive statistical tests to targeted device…”
Get full text

Recent Progress in the Development of High-Density TSV for 3-Layers CMOS Image Sensors by Borel, Stephan, Assous, Myriam, Moreau, Stephane, Velard, Remi

“…Copper TSV in a via last approach were developed for advanced imaging applications. An aspect ratio of 10:1 was targeted with a \boldsymbol{diameter/space} of…”
Get full text

Demonstration of a Wafer Level Face- To-Back (F2B) Fine Pitch Cu-Cu Hybrid Bonding with High Density TSV for 3D Integration Applications by Suarez Berru, Jerzy Javier, Nicolas, Stephane, Bresson, Nicolas, Assous, Myriam, Borel, Stephan

“…We have successfully fabricated a 2-Layers Face-To-Back (F2B) test vehicle (TV) by combining fine pitch Cu-Cu hybrid bonding technology with high density (HD)…”
Get full text

Backside Thinning Process Development for High-Density TSV in a 3-Layer Integration by Bouis, Renan, Marchand, Jeremy, Andre, Agathe, Borel, Stephan, Dechamp, Jerome, Vignoud, Lionel, Valentin, Paul, Assous, Myriam, Hebras, Damien

“…This paper describes recent developments in the field of high density Through Silicon Vias (TSV) with a focus on the backside thinning flow (grinding, CMP,…”
Get full text

Low Resistance and High Isolation HD TSV for 3-Layer CMOS Image Sensors by Borel, Stephan, Assous, Myriam, Velard, Remi, Suarez-Berru, Jerzy-Javier, Nicolas, Stephane, Dechamp, Jerome, Bouis, Renan, Vignoud, Lionel, Valentin, Paul, Marchand, Jeremy, Roman, Antonio, Bedjaoui, Messaoud

“…We developed 1x6μm copper TSV with improved performances in terms of electrical resistance and isolation compared to our formerly published 1x10 μm HD TSV…”
Get full text

3-layer Fine Pitch Cu-Cu Hybrid Bonding Demonstrator With High Density TSV For Advanced CMOS Image Sensor Applications by Nicolas, Stephane, Suarez-Berru, Jerzy-Javier, Bresson, Nicolas, Socquet-Clerc, Carole, Assous, Myriam, Borel, Stephan, Velard, Remi, Dechamp, Jerome, Bouis, Renan, Roman, Antonio, Abadie, Karine, Hebras, Damien

“…After having successfully demonstrating a 2-layer face-to-back (F2B) test vehicle (TV), we reached the next level of integration by achieving a 3-layer TV with…”
Get full text

Advanced 3d Design and Technologies for 3-Layer Smart Imager by Vivet, Pascal, Arnaud, Lucile, Borel, Stephan, Bresson, Nicolas, Assous, Myriam, Nicolas, Stephane, Mauguen, Gaelle, Moreau, Stephane, Altieri, Mauricio, Billoint, Olivier, Thuries, Sebastien, Ollier, Eric

“…CMOS Imagers have adopted 3D integration using Back-Side Illumination (BSI) technology, with 2 CMOS layers assembled using Wafer-to-Wafer and advanced Hybrid…”
Get full text

Process Integration of Photonic Interposer for Chiplet-based 3D Systems by Saint-Patrice, Damien, Malhouitre, Stephane, Assous, Myriam, Pellerin, Thierry, Velard, Remi, Virot, Leopold, Deschaseaux, Edouard, Calvo-Munoz, Maria-Luisa, Hassan, Karim, Bernabe, Stephane, Thonnart, Yvain, Charbonnier, Jean

“…To overpass the bandwidth and the latency limitations of electrical links, the next breakthrough in high performance computing integration will eventually come…”
Get full text

Impact of patterning and ashing on electrical properties and reliability of interconnects in porous SiOCH ultra low-k dielectric materials by Aimadeddine, Mohamed, Arnal, Vincent, Farcy, Alexis, Guedj, Cyril, Chevolleau, Thierry, Possémé, Nicolas, David, Thibaut, Assous, Myriam, Louveau, Olivier, Volpi, Fabien, Torres, Joaquin

“…In this study, a PECVD porous SiOCH dielectric with k = 2.4 is integrated in a Cu single damascene architecture. The main issue investigated is the low k…”
Get full text

Ultra Wide Micro Bumps Interconnection Matrix for High Energy Particle Detection: Process and Assembly by Charbonnier, Jean, Assous, Myriam, Mourier, Thierry, Ribiere, Celine, Minoret, Stephane, Verrun, Sophie, Tissier, Pierre, Coquand, Remi, Bicer, Mehmet, Allain, Fabienne, Franiatte, Remi, Pares, Gabriel

“…Micro pillars and micro bumps interconnections are considered as mature technology for 3-D integration and chip stacking. However, in the framework of…”
Get full text

Bow management with temperature for thin chips integration by Charbonnier, Jean, Assous, Myriam, Bally, Jean-Philippe, Deschaseaux, Edouard, Ratin, Christophe, Hida, Rachid, Poulain, Christophe, Allouti, Nacima, Issele, Helene, Vignoud, Lionel, Moreau, Stephane, Simon, Gilles

“…3D integration and TSV process require chip thinning. For TSV mid process or TSV last, chips with silicon thicknesses below 200μm or even below 100μm are…”
Get full text

Silicon embedded line integration for high end passive silicon interposer by Charbonnier, Jean, Assous, Myriam, Bally, Jean-Philippe, Cuchet, Robert, Mourier, Thierry, Minoret, Stephane, Magis, Thomas, Toffoli, Alain, Allain, Fabienne, Simon, Gilles

“…As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer…”
Get full text

High density 3D silicon interposer technology development and electrical characterization for high end applications by Charbonnier, Jean, Assous, Myriam, Bally, Jean-Philippe, Miyairi, Ken, Sunohara, Masahiro, Cuchet, Robert, Feldis, Helene, Bouzaida, Nicole, Bernard-Henriques, Nathalie, Hida, Rachid, Mourier, Thierry, Simon, Gilles, Higashi, Mitsutoshi

“…As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer…”
Get full text

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits by Cadix, L., Farcy, A., Bermond, C., Fuchs, C., Leduc, P., Rousseau, M., Assous, M., Valentian, A., Roullard, J., Eid, E., Sillon, N., Flechet, B., Ancey, P.

“…Through silicon via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and…”
Get full text

Electrical and morphological characterization for high integrated silicon interposer and technology transfer from 200 mm to 300mm wafer by Sunohara, Masahiro, Miyairi, Ken, Mori, Kenichi, Murayama, Kei, Charbonnier, Jean, Assous, Myriam, Bally, Jean-Philippe, Mourier, Thierry, Minoret, Stephane, Mercier, Denis, Toffoli, Alain, Allain, Fabienne, Martinez, Eugenie, Feldis, Helene, Simon, Gilles, Higashi, Mitsutoshi

“…To achieve high density and high speed transmission between chips, a silicon interposer with copper (Cu) Through Silicon Vias (TSVs) technologies have been…”
Get full text

A successful implementation of dual damascene architecture to copper TSV for 3D high density applications by El Farhane, Rebha, Assous, M, Leduc, P, Thuaire, A, Bouchu, D, Feldis, H, Sillon, N

“…Dual damascene integration was applied to High Density Through Silicon Vias in order to provide a low-cost TSV process. The architecture was developed for 3…”
Get full text

Enabling technologies for 3D chip stacking by Leduc, P., Di Cioccio, L., Charlet, B., Rousseau, M., Assous, M., Bouchu, D., Roule, A., Zussy, M., Gueguen, P., Roman, A., Rozeau, O., Heitzmann, M., Nieto, J.-P., Vandroux, L., Haumesser, P.-H., Quenouillere, R., Toffoli, A., Sixt, P., Maitrejean, S., Clavelier, L., Sillon, N.

“…This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower…”
Get full text

First integration of Cu TSV using die-to-wafer direct bonding and planarization by Leduc, P., Assous, M., Di Cioccio, L., Zussy, M., Signamarcheix, T., Roman, A., Rousseau, M., Verrun, S., Bally, L., Bouchu, D., Cadix, L., Farcy, A., Sillon, N.

“…Copper-filled Through-Si Vias (TSV) with diameters from 2 mum to 5 mum have been integrated in a die-to-wafer stack combining direct bonding and a…”
Get full text