Search Results - "Aseron, Paolo"

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance by Bowman, K A, Tschanz, J W, Lu, S L, Aseron, P A, Khellah, M M, Raychowdhury, A, Geuskens, B M, Tokunaga, C, Wilkerson, C B, Karnik, T, De, V K

“…A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (F CLK ) guardbands for dynamic…”
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A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging by Kulkarni, Jaydeep P., Tokunaga, Carlos, Aseron, Paolo A., Nguyen, Trang, Augustine, Charles, Tschanz, James W., De, Vivek

“…This paper presents an adaptive and resilient domino register file design featuring in-situ timing margin and error detection for the performance-critical…”
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A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications by Paul, Somnath, Honkote, Vinayak, Kim, Ryan Gary, Majumder, Turbo, Aseron, Paolo A., Grossnickle, Vaughn, Sankman, Robert, Mallik, Debendra, Tao Wang, Vangal, Sriram, Tschanz, James W., De, Vivek

“…An energy-harvesting wireless sensor node (WSN) integrates a 14-nm, 0.79-mm 2 , 32-b Intel Architecture corebased near-threshold voltage (NTV) microcontroller…”
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A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS by Jain, S., Khare, S., Yada, S., Ambili, V., Salihundam, P., Ramani, S., Muthukumar, S., Srinivasan, M., Kumar, A., Gb, S. K., Ramanarayanan, R., Erraguntla, V., Howard, J., Vangal, S., Dighe, S., Ruhl, G., Aseron, P., Wilson, H., Borkar, N., De, V., Borkar, S.

“…Near-threshold computing brings the promise of an order of magnitude improvement in energy efficiency over the current generation of microprocessors [1]…”
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All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control by Bowman, K. A., Tokunaga, C., Tschanz, J. W., Raychowdhury, A., Khellah, M. M., Geuskens, B. M., Lu, Shih-Lien L., Aseron, P. A., Karnik, T., De, V. K.

“…A 45 nm microprocessor integrates an all-digital dynamic variation monitor (DVM) to continuously measure the impact of dynamic parameter variations on…”
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2.4 A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots by Honkote, Vinayak, Kurian, Dileep, Muthukumar, Sriram, Ghosh, Dibyendu, Yada, Satish, Jain, Kartik, Jackson, Bradley, Klotchkov, Ilya, Nimmagadda, Mallikarjuna Rao, Dattawadkar, Shreela, Deshmukh, Pranjali, Gupta, Ankit, Timbadiya, Jaykant, Pali, Ravi, Narayanan, Karthik, Soni, Saksham, Chhabra, Saransh, Dhama, Praveen, Sreenivasulu, N., Kollikunnel, Jisna, Kadavakollu, Sureshbabu, Sivaraj, Vijay Deepak, Aseron, Paolo, Azarenkov, Leonid, Robinson, Nancy, Radhakrishnan, Arun, Moiseev, Mikhail, Nandakumar, Ganeshram, Madhukumar, Akhila, Popov, Roman, Sahu, Kamakhya P., Peguvandla, Ramesh, Ruiz, Alberto Del Rio, Bhartiya, Mukesh, Srinivasan, Anuradha, De, Vivek

“…Multi-robot systems, working collectively to accomplish complex missions beyond the capability of a single robot, are required for a wide range of applications…”
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Hyperostosis in orbital rhabdomyosarcoma by Rogelio, Paolo Nico Aseron, Ranche, Felice Katrina Trio, Pe-Yan, Mary Rose

“…Rhabdomyosarcoma is the most common soft-tissue sarcoma in paediatric patients and may arise as a primary orbital neoplasm. Imaging studies show a unilateral…”
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Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor by Dighe, S, Vangal, S R, Aseron, P, Kumar, S, Jacob, T, Bowman, K A, Howard, J, Tschanz, J, Erraguntla, V, Borkar, N, De, V K, Borkar, S

“…In this paper, we present measured within-die core-to-core Fmax and leakage variation data for an 80-core processor in 65 nm CMOS and 1) populate a…”
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A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems by Honkote, Vinayak, Kuttappa, Ragh, Sundaram, Jainaveen, Yada, Satish, Kalimuthu, Chinnusamy, Patil, Juhi, Lee, Richard, Paulino, Cristan, Aseron, Paolo, Nguyen, Trang, Rao, Amreesh, Kurian, Dileep, Xu, Mingming, Song, Yan, Karnik, Tanay, Srinivasan, Anuradha, De, Vivek

“…We present a resonant clocking technique featuring rotary traveling wave oscillators (RTWOs) and a rotary oscillatory array (ROA) in Intel 4 CMOS for…”
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A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications by Paul, Somnath, Honkote, Vinayak, Kim, Ryan Gary, Majumder, Turbo, Aseron, Paolo A., Grossnickle, Vaughn, Sankman, Robert, Mallik, Debendra, Wang, Tao, Vangal, Sriram, Tschanz, James W., De, Vivek

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A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS by Karnik, Tanay, Kurian, Dileep, Aseron, Paolo, Dorrance, Richard, Alpman, Erkan, Nicoara, Angela, Popov, Roman, Azarenkov, Leonid, Moiseev, Mikhail, Li Zhao, Ghosh, Santosh, Misoczki, Rafael, Gupta, Ankit, Akhila, M., Muthukumar, Sriram, Bhandari, Saurabh, Satish, Yada, Jain, Kartik, Flory, Robert, Kanthapanit, Chanitnan, Quijano, Eduardo, Jackson, Bradley, Hao Luo, Suhwan Kim, Vaidya, Vaibhav, Elsherbini, Adel, Renzhi Liu, Sheikh, Farhana, Tickoo, Omesh, Klotchkov, Ilya, Sastry, Manoj, Sheldon Sun, Bhartiya, Mukesh, Srinivasan, Anuradha, Hoskote, Yatin, Hong Wang, Vivek De

“…Energy efficiency, performance and security of compact, self-powered, smart, secure and connected motes at the edge of IoT are critical for realizing…”
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2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology by Somasekhar, D., Yibin Ye, Aseron, P., Shih-Lien Lu, Khellah, M.M., Howard, J., Ruhl, G., Karnik, T., Borkar, S., De, V.K., Keshavarzi, A.

“…We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access…”
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4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging by Kulkarni, Jaydeep P., Tokunaga, Carlos, Aseron, Paolo, Nguyen, Trang, Augustine, Charles, Tschanz, James, De, Vivek

“…8-Transistor (8T) cell 1-read/1-write (1R1W) register files (RF) with domino read and static differential write are critical performance-limiting building…”
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A 3.6GB/s 1.3mW 400mV 0.051mm2 near-threshold voltage resilient router in 22nm tri-gate CMOS by Paul, Somnath, Abbott, Michael, Kishinevsky, Eugene, Aseron, Paolo, Vangal, Sriram, De, Vivek, Taylor, Gregory

“…A 6-port, 2-lane packet-switched input-buffered wormhole router forms the key building block of a 2×2 2D mesh network-on-chip (NoC). The router operates across…”
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Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency by Bowman, Keith, Tokunaga, Carlos, Tschanz, James, Raychowdhury, Arijit, Khellah, Muhammad, Geuskens, Bibiche, Shih-Lien Lu, Aseron, Paolo, Karnik, Tanay, De, Vivek

“…A 45nm microprocessor integrates an all-digital dynamic variation monitor (DVM), consisting of a tunable replica circuit with a time-to-digital converter, to…”
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A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance by Tschanz, J., Bowman, K., Shih-Lien Lu, Aseron, P., Khellah, M., Raychowdhury, A., Geuskens, B., Tokunaga, C., Wilkerson, C., Karnik, T., De, V.

“…A 45 nm 1.3 GHz microprocessor core employs error-detection circuits, tunable replica circuits, and error-recovery circuits, to mitigate dynamic variation…”
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Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor by Dighe, S., Vangal, S., Aseron, P., Kumar, S., Jacob, T., Bowman, K., Howard, J., Tschanz, J., Erraguntla, V., Borkar, N., De, V., Borkar, S.

“…Measured within-die core-to-core F¿¿¿ variation data for an 80-core processor in 65 nm is presented. Variation-aware DVFS with optimal core mapping is shown to…”
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Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops by Raychowdhury, A., Tschanz, J., Bowman, K., Shih-Lien Lu, Aseron, P., Khellah, M., Geuskens, B., Tokunaga, C., Wilkerson, C., Karnik, T., De, V.

“…Built-in resiliency features enable a microprocessor to detect and correct errors due to fast dynamic voltage droop events as well as other types of dynamic…”
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A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction by Jianping Xu, Hazucha, P., Zuoguo Wu, Aseron, P., Mingwei Huang, Paillet, F., Schrom, G., Tschanz, J., De, V., Karnik, T., Taylor, G.

“…The impedance of a microprocessor power-delivery network peaks at ~140 MHz, resulting in power-grid resonance, which lowers operating frequency and compromises…”
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2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process by Somasekhar, Dinesh, Ye, Yibin, Aseron, Paolo, Lu, Shih-Lien, Khellah, Muhammad, Howard, Jason, Ruhl, Greg, Karnik, Tanay, Borkar, Shekhar Y., De, Vivek, Keshavarzi, Ali

“…As silicon technology scales, the possibility of fabricating dense memories is of great interest, particularly if the solution has low to no additional process…”
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