Search Results - "Asenov, P"

A Worst-Case Analysis of Trap-Assisted Tunneling Leakage in DRAM Using a Machine Learning Approach by Lee, J., Asenov, P., Aldegunde, M., Amoroso, S. M., Brown, A. R., Moroz, V.

“…The variability in trap-assisted tunneling leakage that is enhanced by random discrete dopants (RDD) causes refresh failure in scaled 6F 2 dynamic…”
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End-to-end simulation of particle physics events with flow matching and generator oversampling by Vaselli, F, Cattafesta, F, Asenov, P, Rizzi, A

“…Abstract The simulation of high-energy physics collision events is a key element for data analysis at present and future particle accelerators. The comparison…”
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A Two-Prong Approach to the Simulation of DC-RSD: TCAD and SPICE by Croci, T., Menzio, L., Arcidiacono, R., Arneodo, M., Asenov, P., Cartiglia, N., Ferrero, M., Fondacci, A., Monaco, V., Morozzi, A., Moscatelli, F., Mulargia, R., Robutti, E., Sola, V., Passeri, D.

“…The DC-coupled resistive silicon detectors (DC-RSD) are the evolution of the AC-coupled RSD (RSD) design, both based on the low-gain avalanche diode (LGAD)…”
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Multiparty Call Control at the Network Edge by Atanasov, Ivaylo I., Pencheva, Evelina N., Velkova, Denitsa L., Asenov, Ivaylo P.

“…Network programmability is a key feature of fifth generation (5G) system which, in combination with cloud-based services, can support many use cases, including…”
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Can We Ever Get to a 100 nm Tall Library? Power Rail Design for 1nm Technology Node by Moroz, V., Lin, X. W., Asenov, P., Sherlekar, D., Choi, M., Cheng, B., Parikh, S., Chan, Po-Wen, Lee, J. J.

“…We explore six different PR (Power Rail) design options in the range of library cell heights from 100 nm to 130 nm for the 1nm design rules (i.e. CPP…”
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Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits by Asenov, A., Ding, J., Reid, D., Asenov, P., Amoroso, S., Adamu-Lema, F., Gerrer, L.

“…In this paper we will present integrated time dependent variability tool flow that links statistical TCAD simulations, statistical compact model extraction and…”
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Interplay between statistical reliability and variability: A comprehensive transistor-to-circuit simulation technology by Gerrer, L., Millar, C., Asenov, A., Amoroso, S. M., Asenov, P., Ding, J., Cheng, B., Adamu-Lema, F., Markov, S., Asenov, A., Reid, D.

“…In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability…”
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Combining process and statistical variability in the evaluation of the effectiveness of corners in digital circuit parametric yield analysis by Asenov, P, Kamsani, N A, Reid, D, Millar, C, Roy, S, Asenov, A

“…This paper focuses on two main types of MOSFET variability - systematic (process) and statistical (random) variability and discusses the use of process corners…”
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DTCO Launches Moore's Law Over the Feature Scaling Wall by Moroz, V., Lin, X.-W., Asenov, P., Sherlekar, D., Choi, M., Sponton, L., Melvin, L. S., Lee, J., Cheng, B., Nannipieri, A., Huang, J., Jones, S.

“…Instead of marching from one crisply defined technology node to the next with an uncertain timeline, industry is transitioning toward annual technology updates…”
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Heterogeneous Integration Enabled by the State-of-the-Art 3DIC and CMOS Technologies: Design, Cost, and Modeling by Lin, X.-W., Moroz, V., Xu, X., Gao, Y., Rennie, D., Asenov, P., Smidstrup, S., Sherlekar, D., Qin, Z., Fang, T., Lee, J., Choi, M., Jones, S.

“…Heterogeneous integration (HI) opens up a new dimension to improve system-level functionality, performance, power, form factor, and cost. Both 3DIC…”
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Nanowire transistor solutions for 5nm and beyond by Asenov, A., Wang, Y., Cheng, B., Wang, X., Asenov, P., Al-Ameri, T., Georgiev, V. P.

“…In this paper we present a comprehensive computational study of silicon nanowire transistor (SNT) and a SNM SRAM cell based on advanced design technology…”
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A compensated design of the LGAD gain layer by Sola, V., Arcidiacono, R., Asenov, P., Borghi, G., Boscardin, M., Cartiglia, N., Vignali, M. Centis, Croci, T., Ferrero, M., Fondacci, A., Gioachin, G., Giordanengo, S., Lantieri, L., Mandurrino, M., Menzio, L., Monaco, V., Morozzi, A., Moscatelli, F., Passeri, D., Pastrone, N., Paternoster, G., Siviero, F., Staiano, A., Tornago, M.

“…In this contribution, we present an innovative design of the Low-Gain Avalanche Diode (LGAD) gain layer, the p+ implant responsible for the local and…”
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Development and test of innovative Low-Gain Avalanche Diodes for particle tracking in 4 dimensions by Croci, T., Morozzi, A., Asenov, P., Fondacci, A., Moscatelli, F., Passeri, D., Sola, V., Menzio, L., Ferrero, M., Mandurrino, M., Arcidiacono, R., Cartiglia, N., Mulargia, R., Robutti, E., Villarreal, O.A. Marti, Cirio, R., Sacchi, R., Staiano, A., Monaco, V., Arneodo, M.

“…The MIUR PRIN 4DInSiDe collaboration aims at developing the next generation of 4D (i.e., position and time) silicon detectors based on Low-Gain Avalanche…”
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Physical modelling of the SET/RESET characteristics and analog properties of TiOx/HfO2−x/TiOx-based RRAM devices by Bousoulas, P., Asenov, P., Tsoukalas, D.

“…Understanding the origins of switching effect is of great importance, since it can enlighten our perspectives and offers guidance for novel device design. In…”
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2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices by Song, S.C., Colombeau, B., Bauer, M., Moroz, V., Lin, X-W., Asenov, P., Sherlekar, D., Choi, M., Huang, J., Cheng, B., Chidambaram, C., Natarajan, S.

“…We explore four different technology and design options for transistors and library cells for a low power supply voltage of 0.4 V and circuit statistics…”
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Statistical Variability Simulation of Novel Capacitor-less Z2FET DRAM: From Transistor to}Circuit by Duan, M., Cheng, B., Adamu-Lema, F., Asenov, P., Dutta, T., Wang, X., Georgiev, V. P., Millar, C., Pfaeffli, P., Asenov, A.

“…The downscaling of traditional DRAM [1] is facing challenges due to the presence of external capacitor. Z2FET [2-5] has been demonstrated as a promising DRAM…”
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Modelling on Aging Induced Time Dependent Variability of Z2FET for Memory Applications by Duan, M., Cheng, B., Bailon, C. Medina, Adamu-Lema, F, Asenov, P., Millar, C., Pfaeffli, P., Asenov, A.

“…Z2FET is a promising integrated DRAM device to replace the traditional 1 transistor 1 capacitor DRAM [1-4]. Memory products always require minimum cell size,…”
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TCAD proven compact modelling re-centering technology for early 0.x PDKs by Wang, L., Cheng, B., Asenov, P., Pender, A., Reid, D., Adamu-Lema, F., Millar, C., Asenov, A.

“…Well-calibrated predictive TCAD simulations are employed to generate target data for compact models for better pre-V1.0 PDK development. A reliable…”
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An advanced statistical compact model strategy for SRAM simulation at reduced VDD by Asenov, P., Reid, D., Roy, S., Millar, C., Asenov, A.

“…Accurate statistical compact model extraction and circuit simulation are key issues in contemporary SRAM design. The high statistical variability of the small…”
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Fast calculation of capacitances in silicon sensors with 3D and 2D numerical solutions of the Laplace's equation and comparison with experimental data and TCAD simulations by Assiouras, P, Asenov, P, Kyriakis, A, Loukas, D

“…We have developed a software for fast calculation of capacitances in planar silicon pixel and strip sensors, based on 3D and 2D numerical solutions of the…”
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