Search Results - "Arunachalam, Ravishankar"
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A novel algorithm for testing crosstalk induced delay faults in VLSI circuits
Published in 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (2005)“…Crosstalk between adjacent lines can significantly affect the propagation delay of signals in deep-submicron (DSM) circuits. When such a circuit is subjected…”
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Conference Proceeding
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TACO: timing analysis with coupling
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 37th conference on Design automation; 05-09 June 2000 (01-01-2000)“…The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded…”
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Conference Proceeding -
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False coupling interactions in static timing analysis
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation (01-01-2001)“…Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. In order to avoid excessive…”
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Conference Proceeding -
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Static timing analysis with coupling
Published 01-01-2000“…Static timing analysis (STA) tools are used for design sign-off for present-day digital integrated circuits, and occupy a critical position in the design flow…”
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Dissertation -
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Static transition probability analysis under uncertainty
Published in IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings (2004)“…Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation…”
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Conference Proceeding -
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Optimal shielding/spacing metrics for low power design
Published in IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings (2003)“…Noise arising from line-to-line coupling is a major problem for deep submicron design, and present technology trends are causing an increase in this type of…”
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Conference Proceeding -
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Determination of worst-case aggressor alignment for delay calculation
Published in 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) (1998)“…Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need…”
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Conference Proceeding Journal Article -
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Predicting short circuit power from timing models
Published in Proceedings of the 2003 Asia and South Pacific Design Automation Conference (21-01-2003)“…Power dissipation is becoming a major show stopper for integrated circuit design especially in the server and pervasive computing technologies. Careful…”
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Conference Proceeding