Search Results - "Arreghini, A."
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Modeling the Operation of Charge Trap Flash Memory-Part I: The Importance of Carrier Energy Relaxation
Published in IEEE transactions on electron devices (01-01-2024)“…We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS)…”
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A methodology for mechanical stress and wafer warpage minimization during 3D NAND fabrication
Published in Microelectronic engineering (01-02-2022)“…The introduction of the 3D NAND architecture brought new integration challenges, including the impact of fabrication-induced mechanical stress. If not…”
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A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash
Published in IEEE electron device letters (01-12-2022)“…In this letter, a Ni-Al alloy based metal induced lateral crystallization (MILC) process in a vertical Si channel, from 3-D NAND flash cell, is reported…”
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Program charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory
Published in 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (27-09-2021)“…Vertical pitch scaling and channel splitting are under active research to increase bit density in 3D NAND flash memories. Here, we use 3D TCAD simulations to…”
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Conference Proceeding -
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Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND
Published in 2024 IEEE International Reliability Physics Symposium (IRPS) (14-04-2024)“…In this work, we evaluate the scaling limits of inter-word line oxides for 3D NAND Flash devices. We test different oxide stacks by mimicking the stacked…”
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Conference Proceeding -
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Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance
Published in 2024 IEEE International Reliability Physics Symposium (IRPS) (14-04-2024)“…Ferroelectricity boosted gate stacks, such as dual ferroelectric layer and charge trap layer (dual FE-CTL), have been proposed and confirmed to lead to…”
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Conference Proceeding -
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Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices
Published in Solid-state electronics (01-08-2012)“…► Experimental evidence of lateral charge migration in planar device is shown. ► A 2D model able to reproduce the retention transients is developed. ► The…”
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Unexpected artefacts and occult pathologies under CBCT
Published in Oral & implantology (01-04-2017)“…To present the most frequent occult pathologies unexpectedly encountered via cone-beam computed tomography (CBCT), with particular reference to the diagnostic…”
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Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories
Published in IEEE electron device letters (01-01-2010)“…We applied the developed trap spectroscopy by charge injection and sensing to validate the extraction of the silicon nitride trap distribution (both in space…”
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Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory
Published in IEEE electron device letters (01-11-2011)“…A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We…”
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Assessment of tunnel oxide and poly-Si channel traps in 3D SONOS memory before and after P/E cycling
Published in Microelectronic engineering (01-11-2015)“…We comprehensively investigate defects in 3-D SONOS devices (macaroni vs. full channel) in fresh state and after program/erase cycling endurance stress with…”
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3D TCAD Model for Poly-Si Channel Current and Variability in Vertical NAND Flash Memory
Published in 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01-09-2019)“…The polycrystalline nature of state-of-the-art 3D NAND flash channels complicates on-current and variability modeling. We have therefore developed a 3D TCAD…”
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Conference Proceeding -
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Long term charge retention dynamics of SONOS cells
Published in Solid-state electronics (01-09-2008)“…We present a model for charge retention dynamics in SONOS non volatile memory cells which accounts for the space and energy distributions of the trapped charge…”
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Journal Article Conference Proceeding -
14
Experimental and Simulation Analysis of Program/Retention Transients in Silicon Nitride-Based NVM Cells
Published in IEEE transactions on electron devices (01-09-2009)“…A new characterization technique and an improved model for charge injection and transport through ONO gate stacks are used to investigate the program/retention…”
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Electron Trap Profiling Near Al2O3/Gate Interface in TANOS Stack Using Gate-Side Trap Spectroscopy by Charge Injection and Sensing
Published in IEEE electron device letters (01-10-2010)Get full text
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Respiratory disorders in paediatric age: orthodontic diagnosis and treatment in dysmetabolic obese children and allergic slim children
Published in European journal of paediatric dentistry (01-09-2013)“…Obesity and allergic susceptibility are worsening problems in the most industrialised countries. With different mechanisms, they both lead to a deterioration…”
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Application of Single Pulse Dynamics to Model Program and Erase Cycling-Induced Defects in the Tunnel Oxide of Charge-Trapping Devices
Published in 2019 IEEE International Integrated Reliability Workshop (IIRW) (01-10-2019)“…3D NAND, the mainstream technology for high density Flash application [1], is typically based on the charge trapping paradigm, i.e. it relies on the storage of…”
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Conference Proceeding -
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First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices
Published in 2018 IEEE Symposium on VLSI Technology (01-06-2018)“…We are demonstrating for the first time epi-based monocrystalline silicon macaroni channel 3-D NAND devices. The highly controllable channel replacement…”
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Conference Proceeding -
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Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01-12-2018)“…A vertical ferroelectric HfO 2 field effect transistor based on 3-D macaroni NAND architecture is reported for the first time. Up to 2 V memory window was…”
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Conference Proceeding -
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Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells
Published in IEEE transactions on electron devices (01-05-2008)“…We present a broad set of experiments on silicon nitride-based memories aimed at the investigation of the vertical position of the charge trapped in the…”
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