Search Results - "Argyrides, C."

Improving Memory Reliability Against Soft Errors Using Block Parity by Reviriego, P, Argyrides, C, Maestro, J A, Pradhan, D K

“…Memory reliability is an important issue. The continuous scaling of transistor technology enables the use of larger memories making soft errors more likely to…”
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Efficient error detection in Double Error Correction BCH codes for memory applications by Reviriego, P., Argyrides, C., A. Maestro, J.

“…To prevent soft errors from causing data corruption, memories are commonly protected with Error Correction Codes (ECCs). To minimize the impact of the ECC on…”
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On the synthesis of bit-parallel Galois field multipliers with on-line SEC and DED by Mathew, J., Jabir, A. M., Rahaman, H., Argyrides, C., Pradhan, Dhiraj K.

“…In this paper, we present a systematic method for designing single error correcting (SEC) and double error detecting finite field (Galois field) multipliers…”
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Matrix Codes for Reliable and Cost Efficient Memory Chips by Argyrides, C, Pradhan, D K, Kocak, T

“…This paper presents a method to protect memories against multiple bit upsets and to improve manufacturing yield. The proposed method, called a Matrix code,…”
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Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs by Grigoryan, H., Shoukourian, S., Harutyunyan, G., Zorian, Y., Argyrides, C.

“…Automotive innovation is driving the need for built-in reliability, safety and security solutions and architectural design to mitigate emerging threats and,…”
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Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors by Argyrides, C., Reviriego, P., Maestro, J. A.

“…Different techniques have been used to deal with defects and soft errors. Repair techniques are commonly used for defects, while error correction codes are…”
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Multiple Bit Error Detection and Correction in Memory by Tarillo, J F, Mavrogiannakis, N, Lisboa, C A, Argyrides, C, Carro, L

“…Technology evolution provides ever increasing density of transistors in chips, lower power consumption and higher performance. In this environment the…”
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Evaluation of a new low cost software level fault tolerance technique to cope with soft errors by Tarrillo, J F, Lisboa, C A, Carro, L, Argyrides, C, Pradhan, D K

“…Increasing soft error rates make the protection of combinational logic against transient faults in future technologies a major issue for the fault tolerance…”
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Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction by Argyrides, C., Chipana, R., Vargas, F., Pradhan, D. K.

“…This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption…”
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Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories by Argyrides, C., Zarandi, H.R., Pradhan, D.K.

“…This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming…”
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Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors by Argyrides, C., Ferreira, R. R., Lisboa, C. A., Carro, L.

“…A low-overhead technique for correction of induced errors affecting algorithms and their data based on the concepts behind Hamming code is presented and…”
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Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms by Lisboa, C.A., Carro, L., Argyrides, C., Pradhan, D.K.

“…For technologies beyond the 45 nm node, radiation induced transients will last longer than one clock cycle. In this scenario, temporal redundancy techniques…”
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A novel error correction technique for adjacent errors by Argyrides, C., Reviriego, P., Pradhan, D. K., Maestro, J. A.

“…Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to Single Events Upsets (SEUs) has been studied…”
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Improving reliability for bit parallel finite field multipliers using Decimal Hamming by Mavrogiannakis, N, Argyrides, C, Pradhan, D K

“…Technology evolution dictates ever increasing density of transistors in chips, lower power consumption and higher performance. In such environment occurrence…”
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Improved Yield in Nanotechnology Circuits Using Non-square Meshes by Argyrides, C, Mavrogiannakis, N, Pradhan, D K

“…Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires has been predicted to be an alternative to silicon technology since…”
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Highly Reliable Power Aware Memory Design by Argyrides, C., Pradhan, D.K.

“…In this paper, an efficient technique for designing RAMs for on chip correction of double errors integrated on H-tree memory architecture is discussed. The…”
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Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement by Argyrides, C., Vargas, F., Moraes, M., Pradhan, D.K.

“…In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using…”
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A fast error correction technique for matrix multiplication algorithms by Argyrides, C., Lisboa, C.A.L., Pradhan, D.K., Carro, L.

“…Temporal redundancy techniques will no longer be able to cope with radiation induced soft errors in technologies beyond the 45 nm node, because transients will…”
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Multiple SEU tolerance in LUTs of FPGAs using protected schemes by Argyrides, C, Zarandi, H, Pradhan, D K

“…Multiple upsets would be available in SRAM-based FPGAs which utilizes SRAM in different parts to implement circuit configuration and to implement circuit data…”
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Increasing memory yield in future technologies through innovative design by Argyrides, C., Al-Yamani, A., Lisboa, C., Carro, L., Pradhan, D.

“…Future technologies, with ever shrinking devices and higher densities, bring along higher defect rates and lower yield. Memory chips, which are among the…”
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