Search Results - "Apanovich, Y"

Do migration lead to the clash of the values? by M. Y. Apanovich

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Integration of the Migrants in Europe by M. Y. Apanovich

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Numerical simulation of submicrometer devices including coupled nonlocal transport and nonisothermal effects by Apanovich, Y., Blakey, P., Cottle, R., Lyumkis, E., Polsky, B., Shur, A., Tcherniaev, A.

“…Stratton's energy balance model for nonlocal charge transport in semiconductors is extended to include the effects of heterojunctions and lattice heating. The…”
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Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models by Apanovich, Y., Lyumkis, E., Polsky, B., Shur, A., Blakey, P.

“…The differences between two widely used intermediate-level charge transport models are investigated. The origins of the models are reviewed, and mathematical…”
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Non-isothermal analysis of breakdown in SOI transistors by Apanovich, Y., Lyumkis, E., Polsky, B., Blakey, P.

“…Non-isothermal device simulation is used to calculate the drain characteristics of an SOI transistor. The breakdown voltage is found to be lower when lattice…”
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A COMPARISON OF ENERGY BALANCE AND SIMPLIFIED HYDRODYNAMIC MODELS FOR GaAs SIMULATION by Apanovich, Y., Lyumkis, E., Polsky, B., Shur, A., Blakey, P.

“…The use of energy balance and simplified hydrodynamic models for simulating GaAs devices is investigated. The simplified hydrodynamic model predicts velocity…”
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THE INFLUENCE OF LATTICE HEATING ON SEMICONDUCTOR DEVICE CHARACTERISTICS by Apanovich, Y., Cottle, R., Freydin, B., Lyumkis, E., Polsky, B., Tchernaiev, A., Blakey, P.

“…Self-consistent electrothermal simulation of modern semiconductor devices is required for the accurate and efficient design and optimization of many…”
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SPICE parameter extraction and RO validation of a 65nm SOI technology by Goo, J.-S., Chen, Q., Pandey, A., Apanovich, Y., Ly, T., Wason, V., Subba, N., Thuruthiyil, C., Icel, A.B.

“…Accurate extraction of the SPICE model parameter is critical in the CMOS IC design. However, it faces difficult issues in state-of-the-art MOSFET technology…”
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Thermal-aware reliability analysis of nanometer designs by Krishnamoorthy, S, Venkatraman, V, Apanovich, Y, Burd, T, Daga, A

“…Increasing current densities in deep sub-micron designs necessitate accurate power and thermal analysis to help verify compliance with chip-level reliability…”
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Switching constraint-driven thermal and reliability analysis of Nanometer designs by Krishnamoorthy, S, Venkatraman, V, Apanovich, Y, Burd, T, Daga, A

“…As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets…”
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2D Simulation of Heterojunction Devices Including Energy Balance and Lattice Heating by Apanovich, Y., Cottle, R., Lyumkis, E., Polsky, B., Shur, A., Blakey, P.

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Numerical simulation of ultra-thin SOI transistor using non-isothermal energy balance model by Apanovich, Y., Blakey, P., Cottle, R., Lyumkis, E., Polsky, B., Shur, A.

“…Traditional semiconductor device simulators use the drift-diffusion and isothermal (constant lattice temperature) approximations. These can lead to poor…”
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