Search Results - "Aoulaiche, M."

Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory by Popovici, M., Swerts, J., Redolfi, A., Kaczer, B., Aoulaiche, M., Radu, I., Clima, S., Everaert, J.-L., Van Elshocht, S., Jurczak, M.

“…Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are…”
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Random telegraph noise: The key to single defect studies in nano-devices by Simoen, E., Fang, W., Aoulaiche, M., Luo, J., Zhao, C., Claeys, C.

“…A review is given of the different methods to extract the main parameters from a Random Telegraph Signal (RTS) occurring in the channel current of small-area…”
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Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics by dos Santos, S.D., Cretu, B., Strobel, V., Routoure, J.-M., Carin, R., Martino, J.A., Aoulaiche, M., Jurczak, M., Simoen, E., Claeys, C.

“…In this paper, UTBOX nMOSFETs with different gate dielectrics have been studied based on their low-frequency noise (LFN) performance. Since LFN measurements…”
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Low-Frequency-Noise Investigation of n-Channel Bulk FinFETs Developed for One-Transistor Memory Cells by Simoen, E., de Andrade, M. G. C., Aoulaiche, M., Collaert, N., Claeys, C.

“…The low frequency (LF) noise has been studied in n-channel triple-gate bulk fin Field-Effect Transistors (FinFETs), which are developed for one-transistor (1T)…”
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Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell by Collaert, N., Aoulaiche, M., Rakowski, M., Redolfi, A., De Wachter, B., Van Houdt, J., Jurczak, M.

“…In this letter, we demonstrate a one-transistor capacitorless DRAM on standard bulk FinFET, using no additional processing. It is shown that, due to the use of…”
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Analytical model for anomalous Positive Bias Temperature Instability in La-based HfO2 nFETs based on independent characterization of charging components by Toledano-Luque, M., Kaczer, B., Aoulaiche, M., Spessot, A., Roussel, Ph.J., Ritzenthaler, R., Schram, T., Thean, A., Groeseneken, G.

“…•PBTI improvement in HfO2 nFETs achieved by a controlled insertion of La.•Anomalous negative ΔVTH due to charge exchange between high-k and metal…”
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Significant reduction of Positive Bias Temperature Instability in high-k/metal-gate nFETs by incorporation of rare earth metals by Kaczer, B., Veloso, A., Aoulaiche, M., Groeseneken, G.

“…A significant reduction of Positive Bias Temperature Instability (PBTI) in both planar and multiple-gate n-channel FET devices is reported after La and Dy…”
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Impact of Back-Gate Bias and Device Geometry on the Total Ionizing Dose Response of 1-Transistor Floating Body RAMs by Mahatme, N. N., Zhang, E. X., Reed, R. A., Bhuva, B. L., Schrimpf, R. D., Fleetwood, D. M., Linten, D., Simoen, E., Griffoni, A., Aoulaiche, M., Jurczak, M., Groeseneken, G.

“…In this paper we investigate how geometry impacts the memory characteristics of 1-transistor dynamic floating body RAMs (FBRAMs) under total ionizing dose…”
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Stress Memorization Technique-Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process by Ortolland, C., Okuno, Y., Verheyen, P., Kerner, C., Stapelmann, C., Aoulaiche, M., Horiguchi, N., Hoffmann, T.

“…In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS…”
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Reaction-dispersive proton transport model for negative bias temperature instabilities by Houssa, M., Aoulaiche, M., De Gendt, S., Groeseneken, G., Heyns, M. M., Stesmans, A.

“…Negative bias temperature instabilities in p -channel metal-oxide-semiconductor field effect transistors are modeled by taking into account the generation of P…”
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Substrate bias dependency of sense margin and retention in bulk FinFET 1T-DRAM cells by Collaert, N., Aoulaiche, M., De Keersgieter, A., De Wachter, B., Altimime, L., Jurczak, M.

“…► The substrate bias can be used to optimize the retention and sense margin in bulk FinFET 1T-DRAM cells. ► Retention times as high as 2 s with a sense margin…”
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Positive Bias Temperature Instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics by Crupi, F., Pace, C., Cocorullo, G., Groeseneken, G., Aoulaiche, M., Houssa, M.

“…Positive bias temperature instability (PBTI) in nMOSFETs with ultra thin HfSiON gate dielectrics has been investigated. We propose that PBTI is due to electron…”
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Impact of Hf content on negative bias temperature instabilities in HfSiON-based gate stacks by Houssa, M., Aoulaiche, M., Van Elshocht, S., De Gendt, S., Groeseneken, G., Heyns, M. M.

“…The shift of the threshold voltage, Vth, of p-channel metal-oxide-semiconductor field-effect transistors with HfSiON gate stacks, subjected to negative bias…”
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I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration by Ritzenthaler, R., Schram, T., Cho, M. J., Mocuta, A., Horiguchi, N., Thean, A. V.-Y, Spessot, A., Caillat, C., Aoulaiche, M., Fazan, P., Noh, K. B., Son, Y.

“…In this work, the potential of the recently demonstrated D&GR (Diffusion & Gate Replacement, [5]) for thick oxide I/O devices integration is investigated. A…”
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The activation energy dependence on the electric field in UTBOX SOI FBRAM devices by Nicoletti, T., Santos, S. D., Sasaki, K. R. A., Martino, J. A., Aoulaiche, M., Simoen, E., Claeys, C.

“…The dependence of the activation energy on the electric field is investigated in extensionless (underlap) UTBOX FDSOI applied as a single transistor floating…”
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Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications by Sasaki, K.R.A., Nicoletti, T., Almeida, L.M., dos Santos, S.D., Nissimoff, A., Aoulaiche, M., Simoen, E., Claeys, C., Martino, J.A.

“…This work aims to analyze the retention time as a limiting factor for the application of 1T-DRAM cell in future CMOS nodes. Two approaches are proposed in…”
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Electrical Properties of Low-VT Metal-Gated n-MOSFETs Using La2O3/SiOx as Interfacial Layer Between HfLaO High-κ Dielectrics and Si Channel by CHANG, S. Z, YU, H. Y, KEMER, C, ABSIL, P, HOFFMANN, T. Y, BIESEMANS, S, ADELMANN, C, DELABIE, A, WANG, X. P, VAN ELSHOCHT, S, AKHEYAR, A, NYNS, L, SWERTS, J, AOULAICHE, M

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Nitrogen Incorporation in HfSiO(N)/TaN Gate Stacks: Impact on Performances and NBTI by Aoulaiche, M., Houssa, M., Deweerd, W., Trojman, L., Conard, T., Maes, J.W., De Gendt, S., Groeseneken, G., Maes, H.E., Heyns, M.M.

“…Performance and negative-bias temperature instability (NBTI) on atomic-layer-deposited HfSiON metal-gated pMOSFETs are investigated. The impact of nitrogen…”
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A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C by Collaert, N, Aoulaiche, M, De Wachter, B, Rakowski, M, Redolfi, A, Brus, S, De Keersgieter, A, Horiguchi, N, Altimime, L, Jurczak, M

“…Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in…”
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Hot hole induced damage in 1T-FBRAM on bulk FinFET by Aoulaiche, M, Collaert, N, Mercha, A, Rakowski, M, De Wachter, B, Groeseneken, G, Altimime, L, Jurczak, M, Lu, Z

“…The reliability of a one Transistor Floating Body Random Access Memory (1T-FBRAM) bulk FinFET cell using Bipolar Junction Transistor (BJT) programming is…”
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