Search Results - "Andry, P S"

Dry Vertical Alignment Method for Multi-domain Homeotropic Thin-Film-Transistor Liquid Crystal Displays by Cai, C., Lien, A., Andry, P. S., Chaudhari, P., John, R. A., Galligan, E. A., Lacey, J. A., Ifill, H., Graham, W. S., Allen, R. D.

“…Multi-domain homeotropic liquid crystal alignment has been recognized as an alignment method to achieve wide viewing angle for thin-film-transistor liquid…”
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Epitaxial film thickness in the low-temperature growth of Si(100) by plasma enhanced chemical vapor deposition by Varhue, W. J., Rogers, J. L., Andry, P. S., Adams, E.

“…The limiting epitaxial thickness of Si films grown at a low substrate temperature by plasma enhanced chemical vapor deposition has been determined. The…”
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Comparison of diamond-like carbon film deposition by electron cyclotron resonance with benzene and methane by Andry, P. S., Pastel, P. W., Varhue, W. J.

“…A comparative study of the deposition of diamond-like carbon films using methane or benzene in a microwave electron cyclotron resonance plasma-enhanced…”
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Low-temperature homoepitaxial growth of Si by electron cyclotron resonance plasma enhanced chemical vapor deposition by Rogers, J. L., Andry, P. S., Varhue, W. J., McGaughnea, P., Adams, E., Kontra, R.

“…Epitaxial Si films have been deposited at low substrate temperatures of 400 and 500 °C, by plasma enhanced chemical vapor deposition using an electron…”
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2.5D and 3D technology challenges and test vehicle demonstrations by Knickerbocker, J. U., Andry, P. S., Colgan, E., Dang, B., Dickson, T., Gu, X., Haymes, C., Jahnes, C., Liu, Y., Maria, J., Polastre, R. J., Tsang, C. K., Turlapati, L., Webb, B. C., Wiggins, L., Wright, S. L.

“…Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost…”
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IMC bonding for 3D interconnection by Sakuma, K, Sueoka, K, Kohara, S, Matsumoto, K, Noma, H, Aoki, T, Oyama, Y, Nishiwaki, H, Andry, P S, Tsang, C K, Knickerbocker, J U, Orii, Y

“…We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike…”
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An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects by Dickson, T. O., Yong Liu, Rylov, S. V., Bing Dang, Tsang, C. K., Andry, P. S., Bulzacchelli, J. F., Ainspan, H. A., Xiaoxiong Gu, Turlapati, L., Beakes, M. P., Parker, B. D., Knickerbocker, J. U., Friedman, D. J.

“…A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging…”
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3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias by Knickerbocker, J.U., Patel, C.S., Andry, P.S., Tsang, C.K., Buchwalter, L.P., Sprogis, E.J., Hua Gan, Horton, R.R., Polastre, R.J., Wright, S.L., Cotte, J.M.

“…System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage…”
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Atomic-beam alignment of inorganic materials for liquid-crystal displays by Chaudhari, P, Lacey, James, Doyle, James, Galligan, Eileen, Lien, Shui-Chi Alan, Callegari, Alesandro, Hougham, Gareth, Lang, Norton D, Andry, Paul S, John, Richard, Yang, Kei-Hsuing, Lu, Minhua, Cai, Chen, Speidell, James, Purushothaman, Sampath, Ritsko, John, Samant, Mahesh, Stöhr, Joachim, Nakagawa, Yoshiki, Katoh, Yoshimine, Saitoh, Yukito, Sakai, Kazumi, Satoh, Hiroyuki, Odahara, Shuichi, Nakano, Hiroki, Nakagaki, Johji, Shiota, Yasuhiko

“…The technique used to align liquid crystals-rubbing the surface of a substrate on which a liquid crystal is subsequently deposited-has been perfected by the…”
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Investigations of Cu bond structures and demonstration of a wafer-level 3D integration scheme with W TSVs by Chen, K N, Cabral, C, Lee, S H, Andry, P S, Lu, J Q

“…Evaluations of two Cu bond structures, oxide-recessed and lock-n-key, are reported. In addition to excellent electrical characteristics of bonded via chain,…”
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3D silicon integration by Knickerbocker, J.U., Andry, P.S., Dang, B., Horton, R.R., Patel, C.S., Polastre, R.J., Sakuma, K., Sprogis, E.S., Tsang, C.K., Webb, B.C., Wright, S.L.

“…Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration…”
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3D copper TSV integration, testing and reliability by Farooq, M. G., Graves-Abe, T. L., Landers, W. F., Kothandaraman, C., Himmel, B. A., Andry, P. S., Tsang, C. K., Sprogis, E., Volant, R. P., Petrarca, K. S., Winstel, K. R., Safran, J. M., Sullivan, T. D., Chen, F., Shapiro, M. J., Hannon, R., Liptak, R., Berger, D., Iyer, S. S.

“…Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no…”
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3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections by Sakuma, K., Andry, P.S., Dang, B., Maria, J., Tsang, C.K., Patel, C., Wright, S.L., Webb, B., Sprogis, E., Kang, S.K., Polastre, R., Horton, R., Knickerbocker, J.U.

“…In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect…”
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Low temperature growth of Si by PECVD by Varhue, W J, Andry, P S, Rogers, J L, Adams, E, Kontra, R, Lavoie, M

“…PECVD can be used to deposit high quality epitaxial Si films at low substrate temperatures. The most remarkable result of this work is the close similarity…”
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A CMOS-compatible process for fabricating electrical through-vias in silicon by Andry, P.S., Tsang, C., Sprogis, E., Patel, C., Wright, S.L., Webb, B.C., Buchwalter, L.P., Manzer, D., Horton, R., Polastre, R., Knickerbocker, J.

“…In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming…”
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Characterization of micro-bump C4 interconnects for Si-carrier SOP applications by Wright, S.L., Polastre, R., Gan, H., Buchwalter, L.P., Horton, R., Andry, P.S., Sprogis, E., Patel, C., Tsang, C., Knickerbocker, J., Lloyd, J.R., Sharma, A., Sri-Jayantha, M.S.

“…This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and…”
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Characterization of stacked die using die-to-wafer integration for high yield and throughput by Sakuma, K., Andry, P.S., Tsang, C.K., Sueoka, K., Oyama, Y., Patel, C., Dang, B., Wright, S.L., Webb, B.C., Sprogis, E., Polastre, R., Horton, R., Knickerbocker, J.U.

“…We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance…”
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Low temperature growth of Si by PECVD by Varhue, W.J, Andry, P.S, Rogers, J.L, Adams, E, Kontra, R, Lovioe, M

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An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects by Dickson, T. O., Yong Liu, Rylov, S. V., Bing Dang, Tsang, C. K., Andry, P. S., Bulzacchelli, J. F., Ainspan, H. A., Xiaoxiong Gu, Turlapati, L., Beakes, M. P., Parker, B. D., Knickerbocker, J. U., Friedman, D. J.

“…A serial I/O chip set in 45 nm SOI CMOS is mounted via 50 μm pitch micro-C4 bumps to a silicon carrier and communicates over ultra-dense interconnects with…”
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Thermal stress analysis of 3D die stacks with low-volume interconnections by Kohara, S, Sakuma, K, Takahashi, Y, Aoki, T, Sueoka, K, Matsumoto, K, Andry, P S, Tsang, C K, Sprogis, E J, Knickerbocker, J U, Orii, Y

“…Silicon die stacking with low-volume interconnections is an attractive method for 3D integration. It offers such benefits as extension to fine-pitch…”
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