Search Results - "Ando, Hisashige"

Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor by Hisashige Ando, Ryuji Kan, Yoshiharu Tosaka, Takahisa, Keiji, Kichiji Hatanaka

“…The SPARC64 V microprocessor is designed for use in high-reliability, large-scale unix servers. In addition to implementing ECC for large SRAM arrays, the…”
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A 1.3-GHz fifth-generation SPARC64 microprocessor by Ando, H., Yoshida, Y., Inoue, A., Sugiyama, I., Asakawa, T., Morita, K., Muta, T., Motokurumada, T., Okada, S., Yamashita, H., Satsukawa, Y., Konmoto, A., Yamashita, R., Sugiyama, H.

“…A fifth-generation SPARC64 processor is fabricated in 130-nm partially depleted silicon-on-insulator CMOS with eight layers of Cu metallization. At V/sub dd/ =…”
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A case study: power and performance improvement of a chip multiprocessor for transaction processing by Ando, H., Tzartzanis, N., Walker, W.W.

“…Current high-end microprocessor designs focus on increasing instruction parallelism and clock frequency at the expense of power dissipation. This paper…”
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A 1.3GHz fifth generation SPARC64 microprocessor by Ando, Hisashige, Yoshida, Yuuji, Inoue, Aiichiro, Sugiyama, Itsumi, Asakawa, Takeo, Morita, Kuniki, Muta, Toshiyuki, Motokurumada, Tsuyoshi, Okada, Seishi, Yamashita, Hideo, Satsukawa, Yoshihiko, Konmoto, Akihiko, Yamashita, Ryouichi, Sugiyama, Hiroyuki

“…A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 34.7W power dissipation in…”
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Performance prediction of large-scale parallell system and application using macro-level simulation by Susukita, R., Ando, H., Aoyagi, M., Honda, H., Inadomi, Y., Inoue, K., Ishizuki, S., Kimura, Y., Komatsu, H., Kurokawa, M., Murakami, K.J., Shibamura, H., Yamamura, S., Yunqing Yu

“…To predict application performance on an HPC system is an important technology for designing the computing system and developing applications. However,…”
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Performance prediction of large-scale parallell system and application using macro-level simulation by Susukita, Ryutaro, Ando, Hisashige, Aoyagi, Mutsumi, Honda, Hiroaki, Inadomi, Yuichi, Inoue, Koji, Ishizuki, Shigeru, Kimura, Yasunori, Komatsu, Hidemi, Kurokawa, Motoyoshi, Murakami, Kazuaki J., Shibamura, Hidetomo, Yamamura, Shuji, Yu, Yunqing

“…To predict application performance on an HPC system is an important technology for designing the computing system and developing applications. However,…”
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A 64b 4-issue out-of-order execution RISC processor by Shen, G., Patkar, N., Ando, H., Chang, D., Chen, C., Chien Chen, Chen, F., Forssell, P., Gmuender, J., Kitahara, T., Hungwen Li, Lyon, D., Montoye, R., Peng, L., Savkar, S., Sherred, J., Simone, M., Swami, R., Tovey, D., Williams, T.

“…This processor is the first implementation of the SPARC V9 64b instruction set architecture and has an estimated performance exceeding 256 SPECint92 and 330…”
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