Search Results - "Alvandpour, A."

A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode by Mesgarzadeh, B., Alvandpour, A.

“…This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter…”
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Utilizing Process Variations for Reference Generation in a Flash ADC by Sundstrom, T., Alvandpour, A.

“…This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and…”
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Jitter Characteristic in Charge Recovery Resonant Clock Distribution by Mesgarzadeh, B., Hansson, M., Alvandpour, A.

“…This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by…”
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A sub-130-nm conditional keeper technique by Alvandpour, A., Krishnamurthy, R.K., Soumyanath, K., Borkar, S.Y.

“…Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two…”
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A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization by Vangal, S.R., Hoskote, Y.V., Borkar, N.Y., Alvandpour, A.

“…A pipelined single-precision floating-point multiply-accumulator (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save…”
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A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file by Krishnamurthy, R.K., Alvandpour, A., Balamurugan, G., Shanbhag, N.R., Soumyanath, K., Borkar, S.Y.

“…Describes a 256-word 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic…”
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A study of injection locking in ring oscillators by Mesgarzadeh, B., Alvandpour, A.

“…The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage…”
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A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme by Hsu, S., Alvandpour, A., Mathew, S., Shih-Lien Lu, Krishnamurthy, R.K., Borkar, S.

“…This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology. The local bitline uses a…”
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A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors by Alvandpour, A., Krishnamurthy, R.K., Eckerbert, D., Apperson, S., Bloechel, B., Borkar, S.

“…A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7/spl times/ frequency-range and 9ps end-to-end time resolution…”
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Bitline leakage equalization for sub-100nm caches by Alvandpour, A., Somasekhar, D., Krishnamurthy, R., De, V., Borkar, S., Svensson, C.

“…This paper describes a leakage-tolerant circuit technique for embedded sub-100nm SRAM's. The proposed 8-transistor memory cells inject identical leakage…”
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A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- \mum CMOS for Medical Implant Devices by Dai Zhang, Bhide, A., Alvandpour, A.

“…This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design…”
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Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS by Jung, Ylva, Fritzin, J., Enqvist, M., Alvandpour, A.

“…This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method…”
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Design and Analysis of a Class-D Stage With Harmonic Suppression by Fritzin, J., Svensson, C., Alvandpour, A.

“…This paper presents the design and analysis of a low-power Class-D stage in 90 nm CMOS featuring a harmonic suppression technique, which cancels the 3rd…”
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A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS by Sundstrom, T., Svensson, C., Alvandpour, A.

“…This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample rate is achieved through the use of…”
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Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers by Landin, P. N., Fritzin, J., Van Moer, W., Isaksson, M., Alvandpour, A.

“…This paper presents a direct model structure for describing class-D outphasing power amplifiers (PAs) and a method for digitally predistorting these…”
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Low voltage sensing techniques and secondary design issues for sub-90nm caches by Sinha, M., Hsu, S., Alvandpour, A., Burleson, W., Krishnamurthy, R., Borkar, S.

“…CMOS technology and architecture trends are causing the speed of VLSI systems to be increasingly limited by the large capacitance of cache bit-lines and…”
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A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s by Dai Zhang, Alvandpour, A.

“…This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The…”
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A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE by Fritzin, J., Svensson, C., Alvandpour, A.

“…This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS…”
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A high density, low leakage, 5T SRAM for embedded caches by Carlson, I., Andersson, S., Natarajan, S., Alvandpour, A.

“…This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS…”
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A 900 MHz 26.8 dBm differential Class-E CMOS power amplifier by Khan, H R, Wahab, Q, Fritzin, J, Alvandpour, A

“…A 900 MHz differential Class-E amplifier with finite dc inductance has been designed in CMOS. The large inductance of RF choke has been replaced with a finite…”
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