Challenges and opportunities of chip package interaction with fine pitch Cu pillar for 28nm
As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu and LK (Low-k dielectric) material have been introduced to reduce such delays and allow higher device speed and better perfor...
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| Published in: | 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) pp. 47 - 49 |
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| Main Authors: | , , , , , , , , , |
| Format: | Conference Proceeding |
| Language: | English |
| Published: |
IEEE
01-05-2014
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| Subjects: | |
| Online Access: | Get full text |
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| Summary: | As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu and LK (Low-k dielectric) material have been introduced to reduce such delays and allow higher device speed and better performance. However, since dielectric material with low-k value usually possesses large amount of porosity, its mechanical properties are degraded significantly which leads to fragile silicon backend structure. This in turn brings in reliability issues like LK cracking due to CPI (Chip Package Interaction). The application of flip-chip packaging introduces significant amount of mechanical stress on BEOL (Back-End-Of-Line) at chip-attach processing step due to CTE mismatch, and makes CPI much more challenging and critical for silicon integration. At advanced technology nodes, increasing performance demand of mobile processors coupled with SoC integration is one major driver of bump pitch reduction [1]. Higher I/O count can be achieved with finer bump pitch since die size very likely stays constant if not shrinking further. Cu pillar and ELK material have been introduced in 28nm to realize the pitch reduction and performance gain. Small UBM structure is required with fine pitch Cu pillar which introduces large amount of stress in BEOL layers. On the other hand, while k-value of ELK is reduced by ~20% compared to LK used in previous technologies, its hardness and mechanical modulus have been reduced by ~30%, resulting in major reduction of ELK material strength. In this paper, we present our key learnings from 28nm CPI development with fine pitch Cu pillar. Empirical data based on CPI TV as well as mechanical stress simulations are discussed. UBM dimension which is a critical factor with Cu pillar from CPI perspective is searched at fine pitch, and our data shows CPI robustness limits pitch reduction with Cu pillar if using standard mass reflow process. ELK robustness is also tested at different process corners, including UBM size, bump height and Cu etching module. Some ELK marginality issues are discovered at certain process corner combinations. CPI margin at 28nm with fine pitch Cu pillar is then assessed by correlating mechanical stress simulation to thermal shock testing data. It is shown that min ~15% ELK margin in terms of max ELK stress is necessary to ensure no ELK delamination happening at process corners. Impact of IMC (Intermetallic Compound) and Ni barrier are also studied. It is found that growth of IMC is critical for ELK integrity with mass reflow process. Once IMC is fully grown between Cu pillar and substrate bonding pad, since its stiffness is 2~3X higher than Lead-free solder, mechanical stress on ELK layers increases dramatically. Additional work is carried out to minimize the growth of IMC. It is confirmed that addition of Ni barrier effectively suppresses IMC growth, and increases CPI margin at process corners by considerable amount. Detailed data is presented and final recommendations on fine pitch Cu pillar conclude the paper. |
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| ISSN: | 0569-5503 2377-5726 |
| DOI: | 10.1109/ECTC.2014.6897265 |