Search Results - "Albonesi, D. H."

Dynamically tuning processor resources with adaptive processing by Albonesi, D. H., Balasubramonian, R., Dropsbo, S. G., Dwarkadas, S., Friedman, E. G., Huang, M. C., Kursun, V., Magklis, G., Scott, M. L., Semeraro, G., Bose, P., Buyuktosunoglu, A., Cook, P. W., Schuster, S. E.

“…By using adaptive processing to dynamically tune major microprocessor resources, developers can achieve greater energy efficiency with reasonable hardware and…”
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On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions by Haurylau, M., Guoqing Chen, Hui Chen, Jidong Zhang, Nelson, N.A., Albonesi, D.H., Friedman, E.G., Fauchet, P.M.

“…Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication bottleneck in…”
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Dynamically allocating processor resources between nearby and distant ILP by Balasubramonian, Rajeev, Dwarkadas, Sandhya, Albonesi, David H.

“…Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because…”
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Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling by Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Scott, M.L.

“…As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked,…”
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Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor by Magklis, G., Semeraro, G., Albonesi, D.H., Dropsho, S.G., Dwarkadas, S., Scott, M.L.

“…Multiple clock domains is one solution to the increasing problem of propagating the clock signal across increasingly larger and faster chips. The ability to…”
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Front-end policies for improved issue efficiency in SMT processors by El-Moursy, A., Albonesi, D.H.

“…The performance and power optimization of dynamic superscalar microprocessors requires striking a careful balance between exploiting parallelism and hardware…”
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A dynamically tunable memory hierarchy by Balasubramonian, R., Albonesi, D.H., Buyuktosunoglu, A., Dwarkadas, S.

“…The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and…”
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Power-efficient error tolerance in chip multiprocessors by Rashid, M.W., Tan, E.J., Huang, M.C., Albonesi, D.H.

“…The microprocessor industry is rapidly moving to the use of multicore chips as general-purpose processors. Whereas the current generation of chip…”
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Integrating adaptive on-chip storage structures for reduced dynamic power by Dropsho, S., Buyuktosunoglu, A., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Semeraro, G., Magklis, G., Scottt, M.L.

“…Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as…”
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Dynamic data dependence tracking and its application to branch prediction by Lei Chen, Dropsho, S., Albonesi, D.H.

“…To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in…”
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ReMAP: A Reconfigurable Heterogeneous Multicore Architecture by Watkins, M A, Albonesi, D H

“…This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP,…”
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ReMAP: A Reconfigurable Architecture for Chip Multiprocessors by Watkins, M A, Albonesi, D H

“…ReMAP is a reconfigurable architecture for accelerating and parallelizing applications within a heterogeneous chip multiprocessor (CMP). Clusters of cores…”
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A mean value analysis multiprocessor model incorporating superscalar processors and latency tolerating techniques by ALBONESI, D. H, KOREN, I

“…Several approximate mean value analysis shared memory multiprocessor models have been developed and used to evaluate a number of system architectures. In…”
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On-Chip Optical Technology in Future Bus-Based Multicore Designs by Kirman, Nevin, Kirman, Meyrem, Dokania, Rajeev K., Martinez, Jose F., Apsel, Alyssa B., Watkins, Matthew A., Albonesi, David H.

“…This work investigates the integration of CMOS-compatible optical technology to on-chip coherent buses for future CMPs. The analysis results in a hierarchical…”
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Selective cache ways: on-demand cache resource allocation by Albonesi, D.H.

“…Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip…”
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Runtime reconfiguration techniques for efficient general-purpose computation by Bingxiong Xu, Albonesi, D.H.

“…By exploiting hardware partitioning and applying runtime reconfiguration techniques, microprocessor efficiency is significantly improved while retaining high…”
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Reducing the complexity of the register file in dynamic superscalar processors by Balasubramonian, R., Dwarkadas, S., Albonesi, D.H.

“…Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical…”
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STATS : A framework for microprocessor and system-level design space exploration: Microprocessor architecture by ALBONESI, D. H, KOREN, I

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Dynamically managing the communication-parallelism trade-off in future clustered processors by Balasubramonian, Rajeev, Dwarkadas, Sandhya, Albonesi, David H.

“…Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of…”
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Dynamic frequency and voltage control for a multiple clock domain microarchitecture by Semeraro, G., Albonesi, D.H., Dropsho, S.G., Magklis, G., Dwarkadas, S., Scott, M.L.

“…We describe the design, analysis, and performance of an on-line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD)…”
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