Search Results - "Alain, Phommahaxay"

Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging by Inoue, Fumihiro, Phommahaxay, Alain, Gokita, Yohei, Möller, Berthold, Beyne, Eric

“…We used the surface planer process to minimize the within-die and within-wafer nonuniformity caused by the nonoptimized Cu pillar and Si thinning processes…”
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Influence of Si wafer thinning processes on (sub)surface defects by Inoue, Fumihiro, Jourdain, Anne, Peng, Lan, Phommahaxay, Alain, De Vos, Joeri, Rebibis, Kenneth June, Miller, Andy, Sleeckx, Erik, Beyne, Eric, Uedono, Akira

“…[Display omitted] •Mono-vacancy free Si-thinning can be accomplished by combining several thinning techniques.•The grinding damage needs to be removed prior to…”
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Morphological characterization and mechanical behavior by dicing and thinning on direct bonded Si wafer by Inoue, Fumihiro, Podpod, Arnita, Peng, Lan, Phommahaxay, Alain, Rebibis, Kenneth June, Uedono, Akira, Beyne, Eric

“…[Display omitted] •Mechanical behavior of dicing and thinning on direct bonded Si wafer is studied.•Atomic scale defects caused by grinding is removed by…”
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Edge trimming for surface activated dielectric bonded wafers by Inoue, Fumihiro, Jourdain, Anne, Visker, Jakob, Peng, Lan, Moeller, Berthold, Yokoyama, Kaori, Phommahaxay, Alain, Rebibis, Kenneth June, Miller, Andy, Beyne, Eric, Sleeckx, Erik

“…The impact of the edge trimming process on permanently bonded wafers is described. The edge trimming process is a blade sawing process applied on the Si wafer…”
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Process Challenges During CVD Oxide Deposition on the Backside of 20-\mu m Thin 300-mm Wafers Temporarily Bonded to Glass Carriers by Kennes, Koen, Guerrero, Alice, Salahouelhadj, Abdellah, Suhard, Samuel, Derakhshandeh, Jaber, Phommahaxay, Alain, Brems, Steven, Beyer, Gerald, Beyne, Eric

“…A temporary carrier system is evaluated during several backside processing steps on ultra-thin wafers, down to 20\ \mu\mathrm{m} , with the main focus centered…”
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A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage by Iacovo, Serena, D'have, Koen, Okudur, Oguzhan Orkut, De Vos, Joeri, Uhrmann, Thomas, Plach, Thomas, Conard, Thierry, Meersschaut, Johan, Bex, Pieter, Brems, Steven, Phommahaxay, Alain, Gonzalez, Mario, Witters, Liesbeth, Beyer, Gerald, Beyne, Eric

“…Wafer to wafer bonding studies were carried out on blanket and patterned highly warped wafers using SiCN as bonding dielectric material to gain a deeper…”
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Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding by Iacovo, Serena, Peng, Lan, Nagano, Fuya, Uhrmann, Thomas, Burggraf, Jurgen, Fehkuhrer, Andreas, Conard, Thierry, Inoue, Fumihiro, Kim, Soon-Wook, De Vos, Joeri, Phommahaxay, Alain, Beyne, Eric

“…A key factor enabling the reduction of the thermal budget in W2W bonding integration flows is the activation sequence, consisting of cleaning and plasma…”
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Demonstration of a collective hybrid die-to-wafer integration by Suhard, Samuel, Phommahaxay, Alain, Kennes, Koen, Bex, Pieter, Fodor, Ferenc, Liebens, Maarten, Slabbekoorn, John, Miller, Andy, Beyer, Gerald, Beyne, Eric

“…In this paper, a collective hybrid bonding of a die to wafer is demonstrated. The key integration steps such as CMP, wet etch, cleaning, defect metrology,…”
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Introduction of a New Carrier System for Collective Die-to-Wafer Hybrid Bonding and Laser-Assisted Die Transfer by Kennes, Koen, Phommahaxay, Alain, Guerrero, Alice, Bauder, Olga, Suhard, Samuel, Bex, Pieter, Iacovo, Serena, Liu, Xiao, Schmidt, Thomas, Beyer, Gerald, Beyne, Eric

“…Current roadblocks within the collective die-to-wafer bonding flow, limiting die-transfer yield and throughput, are identified and discussed. Based on the…”
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Development of compression molding process for Fan-Out wafer level packaging by Julien, Bertheau, Fabrice F.C., Duval, Tadashi, Kubota, Pieter, Bex, Koen, Kennes, Alain, Phommahaxay, Arnita, Podpod, Eric, Beyne, Andy, Miller, Gerald, Beyer

“…The present study deals with the investigation of compression mold processes and materials to enable a highdensity chip-first multi-die Fan-Out assembly. Wafer…”
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Extremely Low-Force Debonding of Thinned CMOS Substrate by Laser Release of a Temporary Bonding Material by Phommahaxay, Alain, Potoms, Goedele, Verbinnen, Greet, Sleeckx, Erik, Beyer, Gerald, Beyne, Eric, Guerrero, Alice, Dongshun Bai, Xiao Liu, Yess, Kim, Arnold, Kim, Spiess, Walter, Griesbach, Tim, Rapps, Thomas, Lutter, Stefan

“…Over the past few years, temporary bonding has spread together with the development of 3D stacked IC (SIC) technology. Maturity of the various processes has…”
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Design Issues and Considerations for Low-Cost 3-D TSV IC Technology by Van der Plas, G, Limaye, P, Loi, I, Mercha, A, Oprins, H, Torregiani, C, Thijs, S, Linten, D, Stucchi, M, Katti, G, Velenis, D, Cherman, V, Vandevelde, B, Simons, V, De Wolf, I, Labie, R, Perry, D, Bronckers, S, Minas, N, Cupac, M, Ruythooren, W, Van Olmen, J, Phommahaxay, A, de Potter de ten Broeck, M, Opdebeeck, A, Rakowski, M, De Wachter, B, Dehan, M, Nelis, M, Agarwal, R, Pullini, A, Angiolini, F, Benini, L, Dehaene, W, Travaly, Y, Beyne, E, Marchal, P

“…In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is…”
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Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications by Jourdain, A., Buisson, T., Phommahaxay, A., Redolfi, A., Thangaraju, S., Travaly, Y., Beyne, E., Swinnen, B.

“…Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and…”
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High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias by Phommahaxay, Alain, De Wolf, Ingrid, Hoffrogge, Peter, Brand, Sebastian, Czurratis, Peter, Philipsen, Harold, Civale, Yann, Vandersmissen, Kevin, Halder, Sandip, Beyer, Gerald, Swinnen, Bart, Miller, Andy, Beyne, Eric

“…Among the technological developments pushed by the emergence of 3D-ICs, Through Silicon Via (TSV) technology has become a standard element in device processing…”
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Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications by Jourdain, Anne, Phommahaxay, Alain, Verbinnen, Greet, Murdoch, Gayle, Miller, Andy, Rebibis, Kenneth, Guerrero, Alice, McCutcheon, Jeremy, Privett, Mark, Neidrich, Jason, Beyer, Gerald, Beyne, Eric

“…Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding has become a key element in device…”
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Temporary bonding for High-topography Applications: Spin-on Material Versus Dry Film by Jourdain, Anne, Phommahaxay, Alain, Verbinnen, Greet, Guerrero, Alice, Bailey, Susan, Privett, Mark, Arnold, Kim, Miller, Andy, Rebibis, Kenneth, Beyer, Gerald, Beyne, Eric

“…Handling wafers with sub-100 μm thicknesses requires a support or carrier wafer during handling, transport and processing in a semiconductor process line. This…”
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Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding by Huyghebaert, Cedric, Van Olmen, Jan, Civale, Yann, Phommahaxay, Alain, Jourdain, Anne, Sood, Sumant, Farrens, Shari, Soussan, Philippe

“…In this paper we report on the use of Silicon wafer to wafer bonding technology using Trough Silicon Vias (TSV) and Cu to Cu hybrid interconnects. We…”
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Improving the Wafer Thinning Flow Robustness for 2.5D & 3D Applications by Jedidi, Nader, Kennes, Koen, Phommahaxay, Alain, Guerrero, Alice, Beyer, Gerald, Beyne, Eric

“…Packaging technologies (2.5D, 3D) require the thinning of device wafers, down to sub 100 µm in thickness. While using a temporary carrier for that purpose has…”
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Design issues and considerations for low-cost 3D TSV IC technology by Van der Plas, G., Limaye, P., Mercha, A., Oprins, H., Torregiani, C., Thijs, S., Linten, D., Stucchi, M., Guruprasad, K., Velenis, D., Shinichi, D., Cherman, V., Vandevelde, B., Simons, V., De Wolf, I., Labie, R., Perry, D., Bronckers, S., Minas, N., Cupac, M., Ruythooren, W., Van Olmen, J., Phommahaxay, A., de Potter de ten Broeck, M., Opdebeeck, A., Rakowski, M., De Wachter, B., Dehan, M., Nelis, M., Agarwal, R., Dehaene, W., Travaly, Y., Marchal, P., Beyne, E.

“…We investigate key design issues of a low-cost 3D Cu-TSV technology: impact of TSV on MOS devices and interconnect, reliability, thermal hot spots, ESD, signal…”
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Dicing Lane Quality Quantification & Wafer Assessment Using Image Thresholding Techniques by Leech, Damien Jon, Hiro, Akito, Schoofs, Geert, Altintas, Bensu Tunca, Phommahaxay, Alain, Kennes, Koen, Beyer, Gerald, Beyne, Eric

“…The quality of a dicing lane is a qualitative measurement, with many characterization methods available including mechanical and optical profilometry, however…”
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