Search Results - "Aktouf, Chouki"
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Remote testing and diagnosis of System-on-Chips using network management frameworks
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 16-20 Apr. 2007 (16-04-2007)“…This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both…”
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Conference Proceeding
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Towards a Complete SNMP-Based Supervision of System-on-Chips
Published in Journal of network and systems management (01-12-2005)“…This work proposes an adaptation of classical network management protocols for the purpose of a deep testing and management of network-based electronic systems…”
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Towards a Complete SNMP-Based Supervision of System-on-Chips Testing
Published in Journal of network and systems management (2005)Get full text
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An Innovative Methodology for Scan Chain Insertion and Analysis at RTL
Published in 2011 Asian Test Symposium (01-11-2011)“…While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still…”
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Conference Proceeding -
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Towards consistency checking between HDL and UPF descriptions
Published in 2017 Forum on Specification and Design Languages (FDL) (01-09-2017)“…Meeting the requirements of low-power design is a real challenge in the semiconductor industry. In the past few years, many new methodologies have been…”
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Conference Proceeding -
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Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks
Published in 2007 Design, Automation & Test in Europe Conference & Exhibition (01-04-2007)“…This paper presents a new approach that allows remote testing and diagnosis of complex (systems-on-chip) and embedded IP cores. The approach extends both…”
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Conference Proceeding -
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Scan Insertion at the Behavioral Level
Published in International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)Get full text
Conference Proceeding -
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A generic clock controller for low power systems: Experimentation on an AXI bus
Published in 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (01-10-2015)“…Today, high performance and low power consumption are important requirements for the embedded SoCs. The variation in transistors characteristics is increasing…”
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Performance Evaluation of Distributed Diagnosis Algorithms in Parallel Systems
Published in Parallel computing (1998)Get full text
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A complete strategy for testing an on-chip multiprocessor architecture
Published in IEEE design & test of computers (01-01-2002)“…The article proposes an approach that divides testing into three phases: router testing, RAM block testing, and distributed processor testing. This test…”
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A Global Optimization for Scan Chain Insertion at the RT-level
Published in 2011 IEEE Computer Society Annual Symposium on VLSI (01-07-2011)“…We present a new method for scan chain ordering specifically tailored for RTL-scan and its unique challenges…”
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A practical reconfiguration of a 2D massively parallel machine
Published in Proceedings of Twentieth Euromicro Conference. System Architecture and Integration (1994)“…This paper studies fault-tolerant routing algorithms (FTRAs for short) and their implementation strategy in a 2D MIMD machine. We focus on the methodology of…”
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Conference Proceeding -
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Inserting scan at the behavioral level
Published in IEEE design & test of computers (01-07-2000)“…This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it…”
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