Search Results - "Akarvardar, K."

PCM-Based Analog Compute-In-Memory: Impact of Device Non-Idealities on Inference Accuracy by Sun, X., Khwa, W. S., Chen, Y. S., Lee, C. H., Lee, H. Y., Yu, S. M., Naous, R., Wu, J. Y., Chen, T. C., Bao, X., Chang, M. F., Diaz, C. H., Wong, H.-S. P., Akarvardar, K.

“…The impact of phase change memory (PCM) device non-idealities on the deep neural network (DNN) inference accuracy is systematically investigated. Based on the…”
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Characterization of heavily doped SOI wafers under pseudo-MOSFET configuration by Liu, F.Y., Diab, A., Ionica, I., Akarvardar, K., Hobbs, C., Ouisse, T., Mescot, X., Cristoloveanu, S.

“…► The pseudo-MOSFET method is extended for heavily doped SOI wafers. ► An updated model describing the conduction regimes is derived. ► High-dose implantation…”
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Ultralow Voltage Crossbar Nonvolatile Memory Based on Energy-Reversible NEM Switches by Akarvardar, K., Wong, H.-S.P.

“…A novel nonvolatile nanoelectromechanical (NEM) memory (nRAM) is introduced. Differently than the previously proposed NEM memories, the nRAM achieves the…”
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Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor by Akarvardar, K., Cristoloveanu, S., Gentil, P.

“…The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G 4 -FET) are modeled. The 2-D…”
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FINFET technology featuring high mobility SiGe channel for 10nm and beyond by Guo, D., Karve, G., Tsutsui, G., Lim, K.-Y, Robison, R., Hook, T., Vega, R., Liu, D., Bedell, S., Mochizuki, S., Lie, F., Akarvardar, K., Wang, M., Bao, R., Burns, S., Chan, V., Cheng, K., Demarest, J., Fronheiser, J., Hashemi, P., Kelly, J., Li, J., Loubet, N., Montanini, P., Sahu, B., Sankarapandian, M., Sieg, S., Sporre, J., Strane, J., Southwick, R., Tripathi, N., Venigalla, R., Wang, J., Watanabe, K., Yeung, C. W., Gupta, D., Doris, B., Felix, N., Jacob, A., Jagannathan, H., Kanakasabapathy, S., Mo, R., Narayanan, V., Sadana, D., Oldiges, P., Stathis, J., Yamashita, T., Paruchuri, V., Colburn, M., Knorr, A., Divakaruni, R., Bu, H., Khare, M.

“…SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel…”
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Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic by Akarvardar, K., Eggimann, C., Tsamados, D., Singh Chauhan, Y., Wan, G.C., Ionescu, A.M., Howe, R.T., Wong, H.-S.P.

“…An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is…”
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(110) and (100) Sidewall-oriented FinFETs: A performance and reliability investigation by Young, C.D., Akarvardar, K., Baykan, M.O., Matthews, K., Ok, I., Ngai, T., Ang, K.-W., Pater, J., Smith, C.E., Hussain, M.M., Majhi, P., Hobbs, C.

“…► (110) FinFET electron mobility and short channel performance are similar to (100). ► Impact ionization at both drain and source was found to enhance HCI…”
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Analog Nanoelectromechanical Relay With Tunable Transconductance by Akarvardar, K., Wong, H.-S.P.

“…We show by simulation that a three-terminal nanoelectromechanical (NEM) relay combined with a feedback resistor provides a tunable transconductance Gm over an…”
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Investigation of the four-gate action in G(4)-FETs by Dufrene, B, Akarvardar, K, Cristoloveanu, S, Blalock, B J, Gentil, R, Kolawa, E, Mojarradi, M M

“…The four-gate silicon-on-insulator transistor (G(4)-FET) combines MOS and JFET actions in a single transistor to control the drain current. The various…”
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Low-frequency noise in SOI four-gate transistors by Akarvardar, K., Dufrene, B.M., Cristoloveanu, S., Gentil, P., Blalock, B.J., Mojarradi, M.M.

“…Low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G/sup 4/-field-effect transistor] are reported. The noise power spectral…”
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A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors by Akarvardar, K., Mercha, A., Cristoloveanu, S., Gentil, P., Simoen, E., Subramanian, V., Claeys, C.

“…The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator triple-gate transistors is investigated. A complementary…”
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Thin film fully-depleted SOI four-gate transistors by Akarvardar, K., Cristoloveanu, S., Bawedin, M., Gentil, P., Blalock, B.J., Flandre, D.

“…The fully-depleted version of the SOI four-gate transistor (G 4-FET) is introduced and its characteristics are systematically investigated. It is shown that…”
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High-temperature performance of state-of-the-art triple-gate transistors by Akarvardar, K., Mercha, A., Simoen, E., Subramanian, V., Claeys, C., Gentil, P., Cristoloveanu, S.

“…High-temperature performance of state-of-the-art n-channel triple-gate transistors with 15 nm fin-width, 60 nm fin-height, undoped body, high- k gate…”
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A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels by Xie, R., Montanini, P., Akarvardar, K., Tripathi, N., Haran, B., Johnson, S., Hook, T., Hamieh, B., Corliss, D., Wang, J., Miao, X., Sporre, J., Fronheiser, J., Loubet, N., Sung, M., Sieg, S., Mochizuki, S., Prindle, C., Seo, S., Greene, A., Shearer, J., Labonte, A., Fan, S., Liebmann, L., Chao, R., Arceo, A., Chung, K., Cheon, K., Adusumilli, P., Amanapu, H. P., Bi, Z., Cha, J., Chen, H.-C, Conti, R., Galatage, R., Gluschenkov, O., Kamineni, V., Kim, K., Lee, C., Lie, F., Liu, Z., Mehta, S., Miller, E., Niimi, H., Niu, C., Park, C., Park, D., Raymond, M., Sahu, B., Sankarapandian, M., Siddiqui, S., Southwick, R., Sun, L., Surisetty, C., Tsai, S., Whang, S., Xu, P., Xu, Y., Yeh, C., Zeitzoff, P., Zhang, J., Li, J., Demarest, J., Arnold, J., Canaperi, D., Dunn, D., Felix, N., Gupta, D., Jagannathan, H., Kanakasabapathy, S., Kleemeier, W., Labelle, C., Mottura, M., Oldiges, P., Skordas, S., Standaert, T., Yamashita, T., Colburn, M., Na, M., Paruchuri, V., Lian, S., Divakaruni, R., Gow, T., Lee, S., Knorr, A., Bu, H., Khare, M.

“…We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To…”
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Evidence of Radiation-Induced Dopant Neutralization in Partially-Depleted SOI NMOSFETs by Akarvardar, K., Schrimpf, R.D., Fleetwood, D.M., Cristoloveanu, S., Gentil, P., Blalock, B.J.

“…Radiation-induced dopant passivation is evidenced for the first time in partially-depleted SOI n-channel MOSFETs. Isochronal annealing experiments following 10…”
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Investigation of the Four-Gate Action in $hbox G^4$ -FETs by Dufrene, B., Akarvardar, K., Cristoloveanu, S., Blalock, B.J., Gentil, P., Kolawa, E., Mojarradi, M.M.

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Enhanced performance in SOI FinFETs with low series resistance by aluminum implant as a solution beyond 22nm node by Ok, I, Young, C D, Loh, W Y, Ngai, T, Lian, S, Oh, J, Rodgers, M P, Bennett, S, Stamper, H O, Franca, D L, Lin, S, Akarvardar, K, Smith, C, Hobbs, C, Kirsch, P, Jammy, R

“…We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <;20nm, an enhancement of 19% in…”
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Subthreshold slope modulation in G4-FET transistors by DUFRENE, B, BLALOCK, B, CRISTOLOVEANU, S, AKARVARDAR, K, HIGASHINO, T, MOJARRADI, M

“…We describe the operation of the novel SOI four-gate transistor (G4-FET) in the subthreshold region. The subthreshold slope, which may be defined with respect…”
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Scanning the Issue by Wong, H.-S. P., Akarvardar, K., Antoniadis, D., Bokor, J., Hu, C., King-Liu, T.-J., Mitra, S., Plummer, J.D., Salahuddin, S., Deng, L., Li, G., Han, S., Shi, L., Xie, Y., Yaacoub, E., Alouini, M.-S., Douik, A., Dahrouj, H., Al-Naffouri, T.Y.

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Scanning the Issue by Wong, H.-S. P., Akarvardar, K., Antoniadis, D., Bokor, J., Hu, C., King-Liu, T.-J., Mitra, S., Plummer, J.D., Salahuddin, S., Deng, L., Li, G., Han, S., Shi, L., Xie, Y., Yaacoub, E., Alouini, M.-S., Douik, A., Dahrouj, H., Al-Naffouri, T.Y., Alouini, M.-S.

“…This month’s issue offers insight into efficient compression and execution of DNNs, the challenge of connecting rural areas, and the clique problem in wireless…”
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