Process and device performance of a high-speed double poly-Si bipolar technology using borosenic-poly process with coupling-base implant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process...

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Bibliographic Details
Published in:	IEEE transactions on electron devices Vol. 35; no. 8; pp. 1247 - 1256
Main Authors:	Yamaguchi, T., Yu, Y.-C.S., Lane, E.E., Lee, J.S., Patton, E.E., Herman, R.D., Ahrendt, D.R., Drobny, V.F., Yuzuriha, T.H., Garuts, V.E.
Format:	Journal Article
Language:	English
Published:	New York, NY IEEE 01-08-1988 Institute of Electrical and Electronics Engineers
Subjects:	Applied sciences Boron Breakdown voltage Capacitance Cutoff frequency Degradation Delay effects Electronics Exact sciences and technology Implants Leakage current Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Shadow mapping Titanium Performance evaluation Microelectronic fabrication Ion implantation Arsenic Ions Polycrystal Boron Ions Bipolar technology Silicon Transistor emitter
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Summary:	Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4- mu m depth and 1.2- mu m width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Omega /square is discussed.< >
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23
ISSN:	0018-9383 1557-9646
DOI:	10.1109/16.2544