Search Results - "Agarwal, Mayur"

  • Showing 1 - 13 results of 13
Refine Results
  1. 1

    An IEEE single-precision arithmetic based beamformer architecture for phased array ultrasound imaging system by Agarwal, Mayur, Tomar, Abhishek, Kumar, Navneet

    “…Ultrasound imaging is a largely used medical imaging system as it is safe, non-invasive, and capable of real-time imaging. In ultrasound imaging, different…”
    Get full text
    Journal Article
  2. 2

    High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell by Kandpal, Jyoti, Tomar, Abhishek, Agarwal, Mayur, Sharma, K. K.

    “…Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely…”
    Get full text
    Journal Article
  3. 3

    An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System by Agarwal, Mayur, De, Arijit, Banerjee, Swapna

    “…Portable ultrasound systems are useful in point-of-care diagnostic. Improving the image contrast and spatial resolution over a large range of imaging depths…”
    Get full text
    Journal Article
  4. 4

    AN OVERVIEW OF PROSPECTS AND PROBLEMS FOR CONVENTIONAL ELECTRIC MACHINES AND DRIVES FOR THE WIND POWER GENERATION by Mayur Agarwal, Shagufta Khan, Amit Kumar, Preeti Verma, Sunil Dubey, Bishakh Paul

    “…The increasing desire to wind power production systems is a result of rising worries about the energy problem and safeguarding the environment. Researchers and…”
    Get full text
    Journal Article
  5. 5

    Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications by Kandpal, Jyoti, Tomar, Abhishek, Agarwal, Mayur

    Published in Microelectronics (01-09-2021)
    “…Most of the full adder (FA) circuits are implemented through a hybrid logic style using three different modules. The principal peculiarity of these hybrid…”
    Get full text
    Journal Article
  6. 6
  7. 7

    The Smart Early Detection of Addison's Disease Using Time Series Analysis by Saraswat, Nidhi, Agarwal, Mayur, Harron, Syed

    “…This paper proposes a novel early detection gadget for Addison's sickness (ad) using time series analysis. Specifically, it utilizes electrocardiogram (ECG)…”
    Get full text
    Conference Proceeding
  8. 8

    The Smart Improving of Translation Models Using Recurrent Neural Networks by Singh, Anjali, Agarwal, Mayur, J, Gowrishankar

    “…In current years, Recurrent Neural Networks have been gaining increasing attention within the subject of natural language processing. That is because of their…”
    Get full text
    Conference Proceeding
  9. 9

    Evaluating Wavelet Analysis in the Estimation of Network Congestion with Time Series Analysis by S, Adlin Jebakumari, Gupta, Sachin, Agarwal, Mayur

    “…Wavelet analysis is an effective manner to estimate community congestion based on time collection analysis. Wavelet evaluation is an effective sign-processing…”
    Get full text
    Conference Proceeding
  10. 10

    Avoidance of Multi-Machine System Unified Power Flow Controller Transient by G, Sindhu Madhuri, Agarwal, Mayur

    “…A senior member of the flexible AC transmission systems is the unified power flow controller (UPFC). The focus of this research is on the UPFC's consistent…”
    Get full text
    Conference Proceeding
  11. 11

    High Performance 20-T based Hybrid Full Adder using 90nm CMOS Technology by Kandpal, Jyoti, Tomar, Abhishek, Pandey, Kailash, Agarwal, Mayur

    “…In this paper, a high-performance full adder design is proposed using the hybrid logic style. There are three modules in the hybrid logic structure. The module…”
    Get full text
    Conference Proceeding
  12. 12

    VLSI architecture for IEEE single precision floating point moving average calculator by Agarwal, Mayur, Mishra, Ashutosh, Banerjee, Swapna

    “…Moving average is largely used in various image and signal processing applications. Direct calculation of moving average requires a large number of additions…”
    Get full text
    Conference Proceeding
  13. 13

    A new design of low power high speed hybrid CMOS full adder by Agarwal, Mayur, Agrawal, Neha, Alam, Md Anis

    “…We have designed the full Adder using hybrid-CMOS logic style by dividing it in three modules so that it can be optimized at various levels. First module is an…”
    Get full text
    Conference Proceeding