Search Results - "Acosta Alba, P."

Polycrystalline silicon PhC cavities for CMOS on-chip integration by Iadanza, S., Devarapu, G. C. R., Blake, A., Alba, P. Acosta, Pedini, J.-M., O’Faolain, L.

“…In this work, we present an on-chip 2D and 3D photonics integration solution compatible with Front End of Line integration (FEOL) using deposited…”
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Low Temperature Junction Formation for EZ-FET by Zerhouni Abdou, N., Acosta Alba, P., Brunet, L., Milesi, F., Opprecht, M., Gallard, M., Reboh, S., Ionica, I.

“…The EZ-FET is a device with simplified architecture and processing that enables fast electrical characterization of semiconductor films on insulators (SOI)…”
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Investigation of recrystallization and stress relaxation in nanosecond laser annealed Si1−xGex/Si epilayers by Dagault, L., Kerdilès, S., Acosta Alba, P., Hartmann, J.-M., Barnes, J.-P., Gergaud, P., Scheid, E., Cristiano, F.

“…[Display omitted] •Isolated molten island are formed at the onset of melt.•The liquid/solid interface remains rough in partial melt regime.•Relaxation is…”
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Methodology for parameters extraction with undoped junctionless EZ-FETs by Zerhouni Abdou, N., Reboh, S., Brunet, L., Alepidis, M., Acosta Alba, P., Cristoloveanu, S., Ionica, I.

“…The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture…”
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Undoped junctionless EZ-FET: Model and measurements by Zerhouni Abdou, N., Reboh, S., Alepidis, M., Brunet, L., Acosta Alba, P., Cristoloveanu, S., Ionica, I.

“…•An EZFET is a simple and reliable characterization device for substrates and gate stacks.•Junctionless EZFET removes the temperature limitation of junctions…”
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Ex-situ n-type doped carrier-injection layers in direct bandgap GeSn LEDs by Casiez, L., Cardoux, C., Acosta Alba, P., Bernier, N., Richy, J., Pauc, N., Calvo, V., Coudurier, N., Rodriguez, P., Concepción, O., Buca, D., Frauenrath, M., Hartmann, J.M., Chelnokov, A., Reboud, V.

“…The reconstruction of thick GeSn crystalline layers implanted with phosphorus is explored. Our study demonstrates (i) the potential for recrystallizing…”
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Investigation of oxygen penetration during UV nanosecond laser annealing of silicon at high energy densities by Monflier, R., Tabata, T., Rizk, H., Roul, J., Huet, K., Mazzamuto, F., Acosta Alba, P., Kerdilès, S., Boninelli, S., La Magna, A., Scheid, E., Cristiano, F., Bedel-Pereira, E.

“…[Display omitted] •Oxygen and carbon impurities diffusion during melt laser annealing.•Identification and localization of optical defects signatures.•Impact of…”
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Nanosecond laser annealing of pseudomorphic GeSn layers: Impact of Sn content by Frauenrath, M., Acosta Alba, P., Concepción, O., Bae, J.-H., Gauthier, N., Nolot, E., Veillerot, M., Bernier, N., Buca, D., Hartmann, J.-M.

“…Interactions between nanosecond laser pulses and various Sn content pseudomorphic GeSn layers were investigated. The aim was to evaluate the suitability of…”
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A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration by Fenouillet-Beranger, C., Brunet, L., Batude, P., Brevard, L., Garros, X., Casse, M., Lacord, J., Sklenard, B., Acosta-Alba, P., Kerdiles, S., Tavernier, A., Vizioz, C., Besson, P., Gassilloud, R., Pedini, J.-M., Kanyandekwe, J., Mazen, F., Magalhaes-Lucas, A., Cavalcante, C., Bosch, D., Ribotta, M., Lapras, V., Vinet, M., Andrieu, F., Arcamone, J.

“…In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device…”
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Fabrication and Characterization of Boron-Implanted Silicon Superconducting Thin Films on SOI Substrates for Low-Temperature Detectors by Aliane, A., Dussopt, L., Kerdilès, S., Kaya, H., Acosta-Alba, P., Bernier, N., Papon, A.-M., Martinez, E., Veillerot, M., Lefloch, F.

“…In this paper, we discuss the characterization of boron-doped silicon superconducting thin films with a thickness of 70 nm made on silicon-on-insulator…”
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28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analysis by Cavalcante, C., Fenouillet-Beranger, C., Batude, P., Garros, X., Federspiel, X., Lacord, J., Kerdiles, S., Royet, A. S., Acosta-Alba, P., Rozeau, O., Barral, V., Arnaud, F., Planes, N., Sassoulas, P. O., Ghegin, E., Beneyton, R., Gregoire, M., Weber, O., Guerin, C., Arnaud, L., Moreau, S., Kies, R., Romano, G., Rambal, N., Magalhaes, A., Ghibaudo, G., Colinge, J. P., Vinet, M., Andrieu, F.

“…For the first time, the thermal stability of a 28nm FDSOI CMOS technology is evaluated with yield measurements (5Mbit dense SRAM and 1 Million Flip- flops). It…”
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First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration by Fenouillet-Beranger, C., Brunet, L., Batude, P., Brevard, L., Garros, X., Frutuoso, T. Mota, Casse, M., Lugo, J., Lacord, J., Bosch, D., Bernard, N., Magalhaes-Lucas, A., Ribotta, M., Sklenard, B., Milesi, F., Kies, R., Romano, G., Acosta-Alba, P., Kerdiles, S., Tavernier, A., Vizioz, C., Besson, P., Gassilloud, R., Kanyandekwe, J., Cooper, D., Lapras, V., Kim, W. H., Sasaki, Y., Oh, S., Kang, P., Lee, S. W., Na, H., Arcamone, J., Andrieu, F.

“…For the first time FDSOI CMOS transistors with Si- monocrystalline channel have been fabricated at a temperature below 500°C. High performance PMOS…”
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Numerical simulations of nanosecond laser annealing of Si nanoparticles for plasmonic structures by Royet, A-S., Kerdiles, S., Acosta Alba, P., Bonafos, C., Paillard, V., Cristiano, F., Curvers, B., Huet, K.

“…This paper reports numerical simulations of nanosecond laser thermal annealing of plasmonic structures based on Si-nanoparticles embedded in a SiO 2 matrix…”
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RF figures of merit of polysilicon trap-rich layers formed locally by ion amorphization and nanosecond laser annealing by Perrose, M., Alba, P. Acosta, Moulin, M., Augendre, E., Lugo, J., Raskin, J.-P., Reboh, S.

“…We report on polysilicon trap-rich layers fabricated locally by ion implantation and nanosecond laser annealing on high-resistivity Si substrates. Using…”
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EZ-FET junctions activation by nanosecond laser annealing by Abdou, N. Zerhouni, Acosta-Alba, P., Brunet, L., Opprecht, M., Milesi, F., Gallard, M., Reboh, S., Ionica, I.

“…The EZ-FET (easy-FET) is a simple FDSOI-like (Fully Depleted Silicon On Insulator) device that can be used for the electrical characterization of Si layers…”
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3D sequential integration with Si CMOS stacked on 28nm industrial FDSOI with Cu-ULK iBEOL featuring RO and HDR pixel by Mota-Frutuoso, T., Lapras, V., Brunet, L., Basset, L., Lugo, J., Fenouillet-Beranger, C., Vinet, M., Lattard, D., Boulard, F., Exbraya, Y., Boutry, D., Billoint, O., Bosch, D., Maneglia, Y., Peizerat, A., Dumas, S., Sicard, G., Kerdiles, S., Kanyandekwe, J., Sideris, P., Mazzocchi, V., Sarrazin, A., Loup, V., Mauguen, G., Morales, C., Alba, P. Acosta, Balan, V., Perrot, C., Sturm, J., Euvrard, C., Aussenac, F., Janaud, A., Chapon, J-D., Guillermet, M., Guglieri, S., Bailly, F., Toresani, P., Fournel, F., Mouhdach, M., Berthoud, A., Chapelon, L-L., Ribotta, M., Ponthenier, F., Magalhaes, A., Maitrejean, S., Moulin, C., Michailos, J., Arnaud, F., Cathelin, A., Arcamone, J., Andrieu, F., Garros, X., Gaillard, F., Batude, P.

“…This work demonstrates for the first time the 3D sequential integration of CMOS over CMOS with advanced metal line levels (28nm Cu + ULK). The bottom tier…”
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Inter-tier Dynamic Coupling and RF Crosstalk in 3D Sequential Integration by Sideris, P., Lugo-Alvarez, J., Batude, P., Brunet, L., Acosta-Alba, P., Kerdiles, S., Fenouillet-Beranger, C., Sicard, G., Rozeau, O., Andrieu, F., Colinge, J-P., Ghibaudo, G., Theodorou, C.

“…For the first time, an in-depth analysis of the inter-tier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to…”
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Correction: Fabrication and Characterization of Boron-Implanted Silicon Superconducting Thin Films on SOI Substrates for Low-Temperature Detectors by Aliane, A., Dussopt, L., Kerdilès, S., Kaya, H., Acosta-Alba, P., Bernier, N., Papon, A.-M., Martinez, E., Veillerot, M., Lefoch, F.

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Pulsed laser annealing for advanced technology nodes: Modeling and calibration by Huet, K., Aubin, J., Raynal, P.-E., Curvers, B., Verstraete, A., Lespinasse, B., Mazzamuto, F., Sciuto, A., Lombardo, S.F., La Magna, A., Acosta-Alba, P., Dagault, L., Licitra, C., Hartmann, J.-M., Kerdilès, S.

“…•A nanosecond laser annealing TCAD model is calibrated in Ge and SiGe.•Key process metrics for model calibration are extracted.•Key calibration parameters are…”
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Investigation of recrystallization and stress relaxation in nanosecond laser annealed Si 1−x Ge x /Si epilayers by Dagault, L., Kerdilès, S., Acosta-Alba, P, Hartmann, J.-M., Barnes, J.-P., Gergaud, P., Scheid, Emmanuel, Cristiano, Fuccio

“…30 nm-thick pseudomorphic Si1-xGex layers with Ge concentrations x ranging from 0 to 0.4 were submitted to Ultraviolet Nanosecond Laser Annealing (UV-NLA). The…”
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