Search Results - "Achkir, Brice"

Modeling and Analysis of On-Chip Power Noise Induced by an On-Chip Linear Voltage Regulator Module With a High-Speed Output Buffer by Kim, Heegon, Cho, Jonghyun, Yoon, Changwook, Achkir, Brice, Drewniak, James, Fan, Jun

“…In this paper, analytical models of on-chip power noise induced by an on-chip linear voltage regulator module (VRM) circuit with a high-speed output buffer are…”
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Revised L –2 L Method for On-Chip De-Embedding by Erickson, Nicholas, Achkir, Brice, Fan, Jun

“…An evaluation is presented on the L –2 L de-embedding method for on-chip transmission lines. The method is analyzed using measurement data from two chips…”
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Formulation and Network Model Reduction for Analysis of the Power Distribution Network in a Production-Level Multilayered Printed Circuit Board by Shringarpure, Ketan, Siming Pan, Jingook Kim, Jun Fan, Achkir, Brice, Archambeault, Bruce, Drewniak, James L.

“…A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit…”
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Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs by Chulsoon Hwang, Achkir, Brice, Jun Fan

“…The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top…”
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Sensitivity Analysis of a Circuit Model for Power Distribution Network in a Multilayered Printed Circuit Board by Shringarpure, Ketan, Pan, Siming, Jingook Kim, Jun Fan, Achkir, Brice, Archambeault, Bruce, Drewniak, James L.

“…Power distribution network (PDN) design in high speed digital systems is a critical challenge for system performance. Common design methodologies refer to…”
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Modeling and Application of Multi-Port TSV Networks in 3-D IC by Wei Yao, Siming Pan, Achkir, B., Jun Fan, Lei He

“…Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for 3-D integrated circuits (ICs). While…”
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TEM-Like Launch Geometries and Simplified De-embedding for Accurate Through Silicon Via Characterization by de Paulis, Francesco, Piersanti, Stefano, Qian Wang, Jonghyun Cho, Erickson, Nicholas, Achkir, Brice, Jun Fan, Drewniak, James, Orlandi, Antonio

“…Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extract the exact electromagnetic behavior of a through silicon via…”
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Decoupling capacitor power ground via layout analysis for multi-layered PCB PDNs by Zhao, Biyao, Liang, Shuang, Connor, Samuel, Cocchini, Matteo, Achkir, Brice, Ruehli, Albert, Archambeault, Bruce, Fan, Jun, Drewniak, James

“…A modeling methodology to calculate the decoupling capacitor interconnect inductance in a multi-layer PCB is proposed herein. The methodology is based on the…”
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Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer by Chulsoon Hwang, Jingook Kim, Achkir, B., Jun Fan

“…The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The…”
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Novel De-Embedding Methodology and Broadband Microprobe Measurement for Through-Silicon Via Pair in Silicon Interposer by Qian Wang, Jonghyun Cho, Erickson, Nicholas, Chulsoon Hwang, De Paulis, Francesco, Piersanti, Stefano, Orlandi, Antonio, Achkir, Brice, Jun Fan

“…In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) characterization by using a set of simple yet efficient test…”
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Systematic Power Integrity Analysis Based on Inductance Decomposition in a Multi-Layered PCB PDN by Zhao, Biyao, Bai, Siqi, Connor, Samuel, Scearce, Stephen, Cocchini, Matteo, Achkir, Brice, Ruehli, Albert, Archambeault, Bruce, Fan, Jun, Drewniak, James

“…An approach is presented for power integrity analysis on multi-layer printed circuit boards in this paper. Two critical current paths are analyzed. Inductance…”
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On-chip linear voltage regulator module (VRM) effect on power distribution network (PDN) noise and jitter at high-speed output buffer by Heegon Kim, Sukjin Kim, Joungho Kim, Changwook Yoon, Achkir, Brice, Jun Fan

“…In this paper, the reduction of power distribution network noise and jitter at high-speed output buffer by using on-chip linear voltage regulator module…”
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Metaconductor-Based High Signal Integrity Interconnects for 112 Gbps SerDes Interface with Channel Analysis by Kim, Hae-In, Wilcher, Alexander, Jeon, Saeyeong, Pahlavan, Payman, Hsu, Rockwell, Achkir, Brice, Yoon, Yong-Kyu

“…We present a frequency and time domain analysis of Copper/Cobalt metaconductor (Cu/Co-MC) based transmission lines/interconnects for 112 Gbps high-speed…”
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High-Speed Channel Transformer: A Scalable Transformer Network-Based Signal Integrity Simulator by Park, Hyunwook, Ding, Yifan, Zhang, Ling, Bondarenko, Natalia, Ye, Hanqin, Achkir, Brice, Hwang, Chulsoon

“…This article proposes high-speed channel transformer (HSCT), a transformer network-based signal integrity (SI) simulator for high-speed channels…”
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Revised L-2L Method for On-Chip De-Embedding by Erickson, Nicholas, Achkir, Brice, Jun Fan

“…An evaluation is presented on the L-2L de-embedding method for on-chip transmission lines. The method is analyzed using measurement data from two chips…”
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Modeling and Measurement of Ground Bounce Induced by High-Speed Output Buffer With On-Chip Low-Dropout (LDO) Regulator by Kim, Heegon, Cho, Jonghyun, Achkir, Brice, Fan, Jun

“…This study proposes a model of ground bounce induced by a high-speed output buffer with on-chip low-dropout (LDO) regulator. When the output buffer operates…”
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PEEC Modeling in 3D IC/Packaging Applications based on Layered Green's Functions by Zhao, Biyao, Bai, Siqi, Jun, Fan, Achkir, Brice, Ruehli, Albert

“…A circuit modeling application for 3D IC/packages is proposed in this paper. The method is based on the partial element equivalent circuit (PEEC) method and…”
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Optimization of power delivery network design for multiple supply voltages by Siming Pan, Achkir, Brice

“…Great power demands and low-power techniques have increased the requirements on the power delivery network, especially with multiple supply voltages. In this…”
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Investigation of statistical eye-diagram estimation method for HBM including ISI, X-talk, and power noise by Jonghyun Cho, Heegon Kim, Jun Fan, Achkir, Brice

“…Statistical link analysis and link budget calculation is the essential part for current high-speed system design. Because of the difficulty of low bit-error…”
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Comparative study of transmission lines design for 2.5D silicon interposer by Siming Pan, Achkir, Brice

“…In this paper, we present the results of a comparative study performed on six commonly used on-chip differential trace designs in newly emerging 2.5D silicon…”
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