Search Results - "Abreu, Brunno A."

VLSI Design of Tree-Based Inference for Low-Power Learning Applications by Abreu, Brunno A., Grellert, Mateus, Bampi, Sergio

“…The use of Machine Learning techniques in battery-powered devices has increased in recent years. Therefore, evaluating power-accuracy trade-offs of inference…”
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Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers by Wuerdig, Rodrigo N., Sartori, Marcos L. L., Abreu, Brunno A., Bampi, Sergio, Calazans, Ney L. V.

“…This work explores the use of asynchronous approximate multiply-accumulate (MAC) operators and research ways to alleviate the inherent area overhead of such…”
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Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding by Paim, Guilherme, Santana, Gustavo M., Abreu, Brunno A., Rocha, Leandro M. G., Grellert, Mateus, da Costa, Eduardo A. C., Bampi, Sergio

“…The sum of absolute difference (SAD) calculation is one of the most computing-intensive operations in video encoders compatible with recent standards, such as…”
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HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators by Ferreira, Rafael S., Paim, Guilherme, Abreu, Brunno A., Diniz, Claudio M., Costa, Eduardo, Bampi, Sergio

“…The High-Efficiency Video Coding (HEVC) standard introduces a new and complex luminance interpolation filter for fractional-pixel motion estimation. This work…”
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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization by Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Yi, Qingyang, Fujita, Masahiro, Manske, Guilherme B., Pontes, Matheus F., da Rosa, Leomar S., de Aguiar, Marilton S., Butzen, Paulo F., Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R., Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z., de Abreu, Brunno A., de Souza Campos, Isac, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T., Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O., Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, Chatterjee, Satrajit

“…Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area…”
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On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators by de Abreu, Brunno A., Paim, Guilherme, Castro-Godinez, Jorge, Grellert, Mateus, Bampi, Sergio

“…The technology advances in the recent years have led to the spread use of Machine Learning (ML) models in embedded systems. Due to the battery limitations of…”
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Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization by Berndt, Augusto, Campos, Isac S., Lima, Bryan, Grellert, Mateus, Carvalho, Jonata T., Meinhardt, Cristina, De Abreu, Brunno A.

“…Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Traditional approaches…”
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Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design by da Costa, Patricia, Pereira, Pedro T. L., Abreu, Brunno A., Paim, Guilherme, da Costa, Eduardo, Bampi, Sergio

“…This paper reveals that state-of-the-art integer approximate multipliers (AxMs) present dispensable blocks when specifically embedded within a floating-point…”
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A Decision Tree Synthesis Flow for Precise and Approximate Circuits by Campos, Isac S., Berndt, Augusto, de Abreu, Brunno A., Carvalho, Jonata T., Grellert, Mateus, Meinhardt, Cristina

“…Logic and physical synthesis are getting more integrated, aiming to obtain an optimized circuit in terms of delay, power, and area. However, the current…”
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Fast Logic Optimization Using Decision Trees by de Abreu, Brunno A., Berndt, Augusto, Campos, Isac S., Meinhardt, Cristina, Carvalho, Jonata T., Grellert, Mateus, Bampi, Sergio

“…This work evaluates the use of Decision Trees (DTs) methods for a fast logic minimization of Boolean functions. The proposed DT approach is compared to…”
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Physical implementation of an ASIC-oriented SRAM-based viterbi decoder by Rocha, Leandro M. G., Paim, Guilherme, Santana, Gustavo M., Abreu, Brunno A., Ferreira, Rafael, da Costa, Eduardo A. C., Bampi, Sergio

“…Noise plays a key role in data storage and transmission circuits and systems, a threat to data integrity. Hence, it is essential in these circuits to use some…”
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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization by Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Fujita, Qingyang Yi Masahiro, Manske, Guilherme B, Pontes, Matheus F, Junior, Leomar S. da Rosa, de Aguiar, Marilton S, Butzen, Paulo F, Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R, Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z, de Abreu, Brunno A, Campos, Isac de Souza, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T, Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O, Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, Chatterjee, Satrajit

“…Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area…”
Get full text