Search Results - "ARIKADO, T"

First-principles studies of the intrinsic effect of nitrogen atoms on reduction in gate leakage current through Hf-based high-k dielectrics by Umezawa, N., Shiraishi, K., Ohno, T., Watanabe, H., Chikyow, T., Torii, K., Yamabe, K., Yamada, K., Kitajima, H., Arikado, T.

“…The atomistic effects of N atoms on the leakage current through HfO2 high-k gate dielectrics have been studied from first-principles calculations within the…”
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High Density and Low Leakage Current in TiO2 MIM Capacitors Processed at 300 °C by CHENG, C. H, LIN, S. H, CHIN, Albert, JHOU, K. Y, CHEN, W. J, CHOU, C. P, YEH, F. S, HU, J, HWANG, M, ARIKADO, T, MCALISTER, S. P

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Improvement of the Performance of TiHfO MIM Capacitors by Using a Dual Plasma Treatment of the Lower Electrode by Cheng, C.H., Pan, H.C., Huang, C.C., Chou, C.P., Hsiao, C.N., Hu, J., Hwang, M., Arikado, T., McAlister, S.P., Chin, A.

“…We show that a conventional nitrogen plasma treatment is insufficient to suppress the formation of an interfacial layer at the bottom electrode of TiHfO…”
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Improvement of threshold voltage deviation in damascene metal gate transistors by Yagishita, A., Saito, T., Nakajima, K., Inumiya, S., Matsuo, K., Shibata, T., Tsunashima, Y., Suguro, K., Arikado, T.

“…The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the…”
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Evaluation of transistor property variations within chips on 300-mm wafers using a new MOSFET array test structure by Izumi, N., Ozaki, H., Nakagawa, Y., Kasai, N., Arikado, T.

“…A new test structure has been designed to evaluate fluctuations of transistor properties, both within a chip and across a 300-mm wafer. The evaluation system…”
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Physics in Fermi level pinning at the polySi/Hf-based high-k oxide interface by Shiraishi, K., Yamada, K., Torii, K., Akasaka, Y., Nakajima, K., Kohno, M., Chikyo, T., Kitajima, H., Arikado, T.

“…We report that O vacancy (Vo) formation in ionic Hf-based dielectrics and subsequent electron transfer into poly Si gates across the interface, definitely…”
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High Density and Low Leakage Current in \hbox MIM Capacitors Processed at 300 ^ \hbox by Cheng, C.H., Lin, S.H., Jhou, K.Y., Chen, W.J., Chou, C.P., Yeh, F.S., Hu, J., Hwang, M., Arikado, T., McAlister, S.P., Chin, A.

“…We report Ir/TiO 2 /TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum 2 and a leakage current of 3…”
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Open volumes in SiN films for strained Si transistors probed using monoenergetic positron beams by Uedono, A., Ikeuchi, K., Otsuka, T., Ito, K., Yamabe, K., Kohno, M., Moriya, T., Okumura, N., Nakanishi, T., Arikado, T., Ohdaira, T., Suzuki, R.

“…Open volumes in strained SiN films deposited on Si substrates by microwave plasma enhanced chemical vapor deposition were probed using monoenergetic positron…”
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High performance damascene metal gate MOSFETs for 0.1 μm regime by Yagishita, A, Saito, T, Nakajima, K, Inumiya, S, Akasaka, Y, Ozawa, Y, Hieda, K, Tsunashima, Y, Suguro, K, Arikado, T, Okumura, K

“…A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to…”
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Room temperature preparation of activated and crystallized p-type Si1−xGex thin film on glass substrate by intense, pulsed, ion beam evaporation by Hirai, M., Iwashita, R., Arikado, T., Suematsu, H., Jiang, W., Yatsui, K., Takeda, M., Uchitomi, N.

“…A boron doped Si1−xGex thin film has been successfully prepared on a quartz (SiO2) glass substrate at room temperature (RT) by irradiating an intense, pulsed,…”
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Interface reaction of poly-Si/high- k insulator systems studied by hard X-ray photoemission spectroscopy by Ikenaga, E., Hirosawa, I., Kitano, A., Takata, Y., Muto, A., Maeda, T., Torii, K., Kitajima, H., Arikado, T., Takeuchi, A., Awaji, M., Tamasaku, K., Ishikawa, T., Komiya, S., Kobayashi, K.

“…The interface reaction between poly-Si and high- k dielectrics (including HfSiON and HfAlO) have been investigated using hard X-ray ( hν = 5.95 keV)…”
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Agile fab concepts for cost effective and QTAT mini fab by Mikata, Y., Mitsutake, K., Arikado, T., Okumura, K.

“…Recently SoC devices require QTAT and low cost. Also SoC device quickly change its design so that total production amount is not so many. In this situation we…”
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Surface Channel Metal Gate Complementary MOS with Light Counter Doping and Single Work Function Gate Electrode by Nishinohara, Kazumi T., Akasaka, Yasushi, Saito, Tomohiro, Yagishita, Atsushi, Murakoshi, Atsushi, Suguro, Kyoichi, Arikado, Tsunetoshi

“…We propose a channel engineering guideline for the low threshold voltage ( V th ) metal oxide silicon field effect transistor (MOSFET) with metal gate, which…”
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High-k technology towards EOT < 1.0 nm by Arikado, T.

“…In this paper, the author discusses the performance of Hf silicate developed in Selete (the Japanese semiconductor manufacturers consortium, of which the…”
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Oxygen Vacancy Induced Substantial Threshold Voltage Shifts in the Hf-based High- K MISFET with p+poly-Si Gates -A Theoretical Approach by Shiraishi, Kenji, Yamada, Keisaku, Torii, Kazuyoshi, Akasaka, Yasushi, Nakajima, Kiyomi, Konno, Mitsuru, Chikyow, Toyohiro, Kitajima, Hiroshi, Arikado, Tsunetoshi

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Excimer-laser etching on silicon by Horiike, Y., Hayasaka, N., Sekine, M., Arikado, T., Nakase, M., Okano, H.

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Oxygen-vacancy-induced threshold voltage shifts in Hf-related high- k gate stacks by Shiraishi, Kenji, Yamada, Keisaku, Torii, Kazuyoshi, Akasaka, Yasushi, Nakajima, Kiyomi, Konno, Mitsuru, Chikyow, Toyohiro, Kitajima, Hiroshi, Arikado, Tsunetoshi, Nara, Yasuo

“…We have investigated theoretically the cause of the substantial threshold voltage ( V th) shifts observed in Hf-related high- k gate stacks with p+poly-Si…”
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Electrical properties of 0.5 nm thick Hf-silicate top-layer∕HfO2 gate dielectrics by atomic layer deposition by Kamiyama, Satoshi, Miura, Takayoshi, Nara, Yasuo, Arikado, Tsunetoshi

“…The electrical properties have been studied for hafnium (Hf)-based gate stack structures, fabricated using atomic layer deposition (ALD) technology. The very…”
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50 nm gate electrode patterning using a neutral-beam etching system by Noda, Shuichi, Nishimori, Hirotomo, Ida, Tohru, Arikado, Tsunetoshi, Ichiki, Katsunori, Ozaki, Takuya, Samukawa, Seiji

“…A 50-nm-width metal-oxide-semiconductor (MOS) gate etching process was established using a recently-developed neutral-beam etching system by optimizing the gas…”
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Long-lasting organic spasm of the near reflex by Ohashi, T, Kase, M, Hyodo, T, Arikado, T, Suzuki, Y

“…A 57-year-old man was examined after head trauma and found to have long-lasting organic spasm of the near reflex lacking accommodative spasm. Convergence and…”
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