Search Results - "8th International Symposium on Quality Electronic Design (ISQED'07)"

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM by Sato, T., Kunitake, Y.

“…The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research…”
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Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems by Yongpan Liu, Huazhong Yang, Dick, R.P., Wang, H., Li Shang

“…In the past, dynamic voltage and frequency scaling (DVFS) has been widely used for power and energy optimization in embedded system design. As thermal issues…”
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Virtual Channels Planning for Networks-on-Chip by Ting-Chun Huang, Ogras, U.Y., Marculescu, R.

“…The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly…”
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From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis by Singhee, A., Rutenbar, R.A.

“…Problems in computational finance share many of the characteristics that challenge us in statistical circuit analysis: high dimensionality, profound…”
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A TMR Scheme for SEU Mitigation in Scan Flip-Flops by Oliveira, R., Jagirdar, A., Chakraborty, T.J.

“…Radiation from outer space comprising of charged particles can affect transistors in integrated circuits resulting in a change in the state of transistors…”
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Combating NBTI Degradation via Gate Sizing by Xiangning Yang, Saluja, K.

“…NBTI is becoming one of the dominant circuit reliability concerns in nano-scale technologies. We believe that designers can combat NBTI degradation using…”
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Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis by Boule, M., Chenard, J.-S., Zilic, Z.

“…Assertion based design, and more specifically, assertion based verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are…”
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Modeling of PMOS NBTI Effect Considering Temperature Variation by Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie

“…Negative bias temperature instability (NBTI) has come to the forefront of critical reliability phenomena in advanced CMOS technology. In this paper, we propose…”
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Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays by Do, M.Q., Drazdziulis, M., Larsson-Edefors, P., Bengtsson, L.

“…We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer…”
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Variation Impact on SER of Combinational Circuits by Ramakrishnan, K., Rajaraman, R., Suresh, S., Vijaykrishnan, N., Xie, Y., Irwin, M.J.

“…Increasing variability not only affects the behavior of contemporary ICs but also their vulnerability to transient error phenomenon especially radiation…”
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Dynamic Power Management by Combination of Dual Static Supply Voltages by Agarwal, K., Nowka, K.

“…Energy efficient computing is a first order design concern in portable devices. This paper describes a design approach that enables operation of a processor in…”
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Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology by Alam, S.M., Jones, R.E., Rauf, S., Chatterjee, R.

“…In a general case of 3D integrated circuit (IC) technology, it is desirable to design a die for 3D integration with flexibility to facilitate integration with…”
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Self-Adaptive Systems to Drive out the Nano-Scale Devil by Pol, Marcal

“…Within 15 years we will reach the ultimate scaling of CMOS.This will enable the billion transistor chips needed for ever more complex ambient intelligent…”
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Expression of Concern: Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization by Alam, Mehboob, Nieuwoudt, Arthur, Massoud, Yehia

“…Model order reduction plays a key role in determining VLSI system performance and the optimization of interconnects. In this paper, we develop an accurate and…”
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Expression of Concern: Parameter-Variation-Aware Analysis for Noise Robustness by Mondal, Mosin, Mohanram, Kartik, Massoud, Yehia

“…This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled…”
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Expression of Concern: Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations by Nieuwoudt, Arthur, Ragheb, Tamer, Nejati, Hamid, Massoud, Yehia

“…In this paper, we develop several design techniques for reducing the impact of manufacturing variations on integrated wideband low noise amplifiers (LNA)…”
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Quality Driven Manufacturing and SOC Designs by Venkataraman, Srikanth, Nagapalli, Nagesh, Jozwiak, Lech

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DFT and Test: Ensuring Product Quality by Nagapalli, Nagesh

“…Once design changes are made for DFM/DFY, it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed…”
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SUB 45nm Low Power Design Challenges by Tschanz, James W.

“…The ever-increasing use of mobile devices and the constant desire for energy efficiency and long battery life have made low power design more important than…”
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Multi-Gate MOSFET Design by Knoblinger, Gerhard

“…Multi-Gate Field Effect Transistors (MuGFET) such as FinFETs and Triple-Gate FETs are the most promising device structures for sub-45nm CMOS technology…”
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