Search Results - "26th ACM/IEEE Design Automation Conference"

Efficient algorithms for computing the longest viable path in a combinational network by McGeer, P. C., Brayton, R. K.

“…We consider the elimination of false paths in combinational circuits. We give the single generic algorithm that is used to solve this problem, and demonstrate…”
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IRSIM: an incremental MOS switch-level simulator by Salz, A., Horowitz, M.

“…This paper describes IRSIM, an incremental switch-level simulator for MOS transistor circuits. In IRSIM, the circuit under simulation can be modified and then…”
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NOVA: state assignment of finite state machines for optimal two-level logic implementations by Villa, T., Sangiovanni-Vincentelli, A.

“…The problem of encoding the states of a synchronous Finite State Machine (FSM), so that the area of a two-level implementation of the combinational logic is…”
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Performance-driven placement of cell based IC's by Jackson, M. A. B., Kuh, E. S.

“…The increasingly important role of the interconnect in the timing performance of present and future integrated circuit technologies underscores the need to…”
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On the general false path problem in timing analysis by Du, D. H., Yen, S. H., Ghanta, S.

“…The false path problem is often referred to as the problem of detecting the longest sensitizable path (A path which is not a false path is a sensitizable…”
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Scheduling and binding algorithms for high-level synthesis by Paulin, P. G., Knight, J. P.

“…New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list…”
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Loop optimization in register-transfer scheduling for DSP-systems by Goossens, G., Vandewlle, J., De Man, H.

“…In this paper, we discuss a control-flow transformation called loop folding, during the scheduling of register-transfer code for DSP-systems. Loop folding is…”
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Automatic sizing of power/ground (P/G) networks in VLSI by Dutta, R., Marek-Sadowska, M.

“…This paper presents a fast and efficient method for sizing power/ground networks. No restrictions on network topology or number of supplying pads are imposed…”
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Efficient algorithms for extracting the K most critical paths in timing analysis by Yen, S. H., Du, D. H., Ghanta, S.

“…Path extracting algorithms are a very important part of timing analysis approach. In this paper we designed and developed several algorithms which can generate…”
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A functional-level test generation methodology using two-level representations by Davé, U. J., Patel, J. H.

“…This paper proposes the use of a functional-level testing methodology based on the generation of test vectors from the functional descriptions of combinational…”
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Parallel pattern fault simulation of path delay faults by Schulz, M., Fink, F., Fuchs, K.

“…This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in…”
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A comparison of four two-dimensional gate matrix layout tools by Irwin, M. J., Owens, R. M.

“…A comparison of four layout tools is presented. The layout style is a two-dimensional gate matrix. The first layout tool discussed uses "standard" simulated…”
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Integrated scheduling and binding: a synthesis approach for design space exploration by Balakrishnan, M., Marwedel, P.

“…Synthesis of digital systems, involves a number of tasks ranging from scheduling to generating interconnections. The interrelationship between these tasks…”
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A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing by Wen-Ben Jone, Papachristou, C.A.

“…In this work, we propose a circuit partitioning and test pattern generation algorithm for built-in pseudoexhaustive self-testing of VLSI circuits. The circuit…”
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A New Approach to the Rectilinear Steiner Tree Problem by Jan-ming Ho, Vijayan, G., Wong, C.K.

“…We discuss a new approach to constructing the rectilinear Steiner tree (RST) of a given set of points in the plane, starting from a minimum spanning tree…”
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iSMILE: a novel circuit simulation program with emphasis on new device model development by Yang, A. T., Kang, S. M.

“…The laborious task of implementing a new device model in a circuit simulator has long been recognized as a painful bottleneck to device modeling. In contrast…”
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GENAC: An Automatic Cell Synthesis Tool by Chong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo

“…We present a solution to the layout problem of cell synthesis, which achieves multiple optimization objectives. In particular, we propose a new hierarchical…”
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Tutorial/Panel: Competitive Design Methodologies for ASICs by Allen, J.

“…This large market for application-specific integrated circuits (ASIC's) creates a need for IC design methods that are capable of producing ICs quickly and with…”
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The Last Decade of Design Automation. And the next by Langler, G.

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Tutorial/Panel Case for Electronic Design Automation by Rappaport, A.

“…A decade ago, it was possible for a talented design engineer or computer programmer to devise a simple but effective tool as an aid in the design of electronic…”
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