Search Results - "2024 25th International Symposium on Quality Electronic Design (ISQED)"

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  1. 1

    Bring it On: Kinetic Energy Harvesting to Spark Machine Learning Computations in IoTs by Shukla, Sanket, Dinakarrao, Sai Manoj Pudukottai

    “…The widespread adoption of Internet of Things (IoTs) and edge computing devices has made them an integral part of our daily lives. The popularity of these…”
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    Conference Proceeding
  2. 2

    Trojan Assets and Attack Vectors in Processors by Chuah, Czea Sie, Hepp, Alexander, Appold, Christian, Leinmueller, Tim

    “…Processor design and manufacturing is often done globally, involving multiple companies, some of which can be untrustworthy. This lack of trust leads to the…”
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    Conference Proceeding
  3. 3

    Hyperdimensional Computing vs. Neural Networks: Comparing Architecture and Learning Process by Ma, Dongning, Hao, Cong, Jiao, Xun

    “…Hyperdimensional Computing (HDC) has obtained abundant attention as an emerging non von Neumann computing paradigm. Inspired by the way human brain functions,…”
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    Conference Proceeding
  4. 4

    SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization by Jeon, Joong-Won, Kahng, Andrew B., Kang, Jae-Hyun, Kim, Jaehwan, Woo, Mingyu

    “…Reducing design rule check (DRC) violations, subject to meeting performance, area and schedule targets, has always been the key metric for VLSI physical…”
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    Conference Proceeding
  5. 5

    Learning Client Selection Strategy for Federated Learning across Heterogeneous Mobile Devices by Zhang, Sai Qian, Lin, Jieyu, Zhang, Qi, Chen, Yu-Jia

    “…The rapid growth of Internet of Things have yielded a remarkable increase in the volume of the data generated on client devices. This technological trend…”
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    Conference Proceeding
  6. 6

    Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs by Gu, Zhengyao, Lopez, Diego Troy, Alrahis, Lilas, Sinanoglu, Ozgur

    “…Graph neural network-based network intrusion detection systems have recently demonstrated state-of-the-art performance on benchmark datasets. Nevertheless,…”
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    Conference Proceeding
  7. 7

    RTKWS: Real-Time Keyword Spotting Based on Integer Arithmetic for Edge Deployment by Dhungana, Prakash, Salehi, Sayed Ahmad

    “…This paper presents an efficient real-time keyword spotting (RTKWS) architecture for edge devices. The proposed architecture comprises data acquisition (DA),…”
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    Conference Proceeding
  8. 8

    Obfuscating Quantum Hybrid-Classical Algorithms for Security and Privacy by Upadhyay, Suryansh, Ghosh, Swaroop

    “…As quantum computing gains popularity, it's crucial to tackle security and privacy issues upfront. One major concern is the involvement of third-party tools…”
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  9. 9

    RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware by Kundu, Shamik, Raha, Arnab, Mathaikutty, Deepak A., Basu, Kanad

    “…In this paper, we present a novel sparsity-based acceleration logic, that leverages both-sided fine-grained sparsity in the activation and weight tensors to…”
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  10. 10

    Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators by Taheri, Mahdi, Cherezova, Natalia, Ansari, Mohammad Saeed, Jenihhin, Maksim, Mahani, Ali, Daneshtalab, Masoud, Raik, Jaan

    “…The stringent requirements for the Deep Neural Networks (DNNs) accelerator's reliability stand along with the need for reducing the computational burden on the…”
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    Conference Proceeding
  11. 11

    Thermo-Attack Resiliency: Addressing a New Vulnerability in Opto-Electrical Network-on-Chips by Hasanzadeh, Mahdi, Abdollahi, Meisam, Baniasadi, Amirali, Patooghy, Ahmad

    “…Optical Network-on-Chip (ONoC) has recently emerged as a power- and latency-efficient solution to improve the performance of Multi-Processor System-on-Chips…”
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    Conference Proceeding
  12. 12

    TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments by Forcioli, Quentin, Chaudhuri, Sumanta, Danger, Jean-Luc

    “…In this article, we present a tool to analyze cache timing vulnerabilities in trusted execution environments. First, we present a platform based on the…”
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    Conference Proceeding
  13. 13

    SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning by Liu, Siqin, Karanth, Avinash

    “…The ability to automatically generate a neural network architecture and the corresponding hardware implementation to optimize both accuracy and performance…”
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    Conference Proceeding
  14. 14

    BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture by Veluri, Hasita, Vasudevan, Dilip

    “…An FPCA (Field-Programmable Crossbar Array) architecture based on memristors offers improved programmability while blurring the line between computing and…”
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  15. 15

    Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach by Gowda, Bindu G, Prashanth, H C, Muralidhara, V N, Rao, Madhav

    “…Approximation in arithmetic computations is accepted widely in error-resilient image and signal processing applications, in which the computation time is more…”
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  16. 16

    sLLM: Accelerating LLM Inference using Semantic Load Balancing with Shared Memory Data Structures by Lin, Jieyu, Zhang, Sai Qian, Leon-Garcia, Alberto

    “…As Large Language Models (LLMs) are increasingly deployed to support a broad spectrum of applications, enhancing inference efficiency and minimizing costs have…”
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    Conference Proceeding
  17. 17

    Temporal-encoded 6T-RRAM with Bidirectional Control for Future Neuromorphic Systems by Bai, Kang Jun, Jiang, Hao, Qin, Zhuwei, Thiem, Clare

    “…Neuromorphic systems are of high importance in artificial intelligence (AI) to eschew challenges inherent to deep learning acceleration in conventional…”
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    Conference Proceeding
  18. 18

    Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives by Akiyama, Soramichi, Shioya, Ryota, Miyatake, Yuto, Yang, Tongxin

    “…Fixed-point arithmetic is widely used because of its efficiency in latency, area, and power consumption. However, determining the number of bits assigned to…”
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  19. 19

    Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats by Basavaraju, Mahati, Rayapati, Vinay, Rao, Madhav

    “…With the increase in demand for neural networks (NNs) on edge devices, there is a need for cost-effective and hardware-efficient architectures. Activation…”
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  20. 20

    Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology by Karn, Rupesh Raj, Knechtel, Johann, Sinanoglu, Ozgur

    “…Confidential inference (CI) involves leveraging data encryption to safeguard privacy while allowing inference on encrypted data. Various cryptographic methods,…”
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    Conference Proceeding