Search Results - "2023 IEEE Nordic Circuits and Systems Conference (NorCAS)"

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  1. 1

    neuroAIx: FPGA Cluster for Reproducible and Accelerated Neuroscience Simulations of SNNs by Kauth, Kevin, Stadtmann, Tim, Sobhani, Vida, Gemmeke, Tobias

    “…The complex mechanisms and impressive learning capabilities of the human brain inspire the search for ever more efficient neural network models. Investigating…”
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    Conference Proceeding
  2. 2

    Reliable Code-Based Post-Quantum Cryptographic Algorithms through Fault Detection on FPGA by Cintas-Canto, Alvaro, Mozaffari-Kermani, Mehran, Azarderakhsh, Reza

    “…Code-based cryptography is a promising post-quantum cryptographic solution against attacks enabled by classical and quantum computers. The Niederreiter…”
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  3. 3

    Effective Processor Model Generation from Instruction Set Simulator to Hardware Design by Kappes, Johannes, Kunzelmann, Robert, Emrich, Karsten, Foik, Conrad, Mueller-Gritschneder, Daniel, Ecker, Wolfgang

    “…As the complexity of modern processing systems continues to increase, there has been a growing interest in the application of reusable code generators for…”
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  4. 4

    A complete SHA-3 hardware library based on a high efficiency Keccak design by Camacho-Ruiz, Eros, Sanchez-Solano, Santiago, Martinez-Rodriguez, Macarena C., Brox, Piedad

    “…Hash functions are a crucial part of the cryptographic primitives. So much so that in 2007 a new competition was launched to select new standards for the SHA-3…”
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    Conference Proceeding
  5. 5

    Cell-Based Aging Sensor Using Built-In Speed Grading by Lin, Ont-Derh, Huang, Shi-Yu

    “…Built-In Speed Grading (BISG) is a technique that measures the maximum operating speed (Fmax) of a circuit under test in silicon. Traditionally, it has been…”
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  6. 6

    A Low-Power Current-Reuse Self-Biased Regulated-Cascode TIA in 130nm SiGe BiCMOS for Low-Noise and High Data Rate Applications by Abdollahi, Behnam, Zimmermann, Horst

    “…This paper presents a 35 Gbps, current-reuse, self-biased regulated cascode (RGC) transimpedance amplifier (TIA). Thanks to an RC N -degeneration Wilson…”
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  7. 7

    Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism by Vohra, Sahibia Kaur, James, Alex P., Sakare, Mahendra, Das, Devarshi Mrinal

    “…The aim of designing the energy-efficient high-density spiking neural network (SNN) is not possible without channelising the efforts to design the basic…”
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  8. 8

    Active Wideband 55-100-GHz Downconversion Mixer in 22-nm FDSOI CMOS by Jokiniemi, Kimi, Ryynanen, Kaisa, Vaha, Joni, Kankkunen, Elmo, Stadius, Kari, Ryynanen, Jussi

    “…This paper presents a wideband active CMOS downconversion mixer for emerging mmWave communication and sensing applications. The designed mixer utilizes…”
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  9. 9

    Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators by Cromjongh, Casper, Tian, Yongding, Hofstee, Peter, Al-Ars, Zaid

    “…In spite of progress on hardware design languages, the design of high-performance hardware accelerators forces many design decisions specializing the…”
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  10. 10

    AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management by Leppanen, Topi, Multanen, Joonas, Leppanen, Leevi, Jaaskelainen, Pekka

    “…OpenCL provides a consistent programming model across CPUs, GPUs, and FPGAs. However, to get reasonable performance out of FPGAs, OpenCL programs created for…”
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  11. 11

    High-Performance Floating Resistor-based Ring Amplifier for Switched Capacitor Circuits by Pundir, Manish, Singh, Bipul Kumar, Kamble, Ninad Bandu, Shah, Ambika Prasad

    “…This paper presents a modified bias-enhanced with a floating resistor ring amplifier (FR-RAMP) circuit. The design uses two transistor-based floating resistor…”
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  12. 12

    An IMPLY-based Semi-Serial Approximate In-Memristor Adder by Seiler, Fabian, TaheriNejad, Nima

    “…To alleviate the Von Neumann bottleneck, new technologies and computing paradigms have been a hot topic in research and development in recent years. Memristors…”
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  13. 13

    Toward All-Digital Time-Domain Neural Network Accelerators for In-Sensor Processing Applications by Mohey, Ahmed M., Kosunen, Marko, Ryynanen, Jussi, Andraud, Martin

    “…Deep Neural Network (DNN) accelerators are increasingly integrated into sensing applications, such as wearables and sensor networks, to provide advanced…”
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  14. 14

    High-level FPGA Design of Deep Learning Hyperspectral Anomaly Detection by Boyle, Samuel, Gunderson, Aksel, Orlandic, Milica

    “…Hyperspectral image Anomaly Detection (HSI-AD) has attracted considerable attention in the field of remote sensing. With improved detection accuracy, as a…”
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  15. 15

    Control Plane Isolation of Network Security Protocols using FPGA-SoC Trusted Execution Environment by Dik, Daniel, Berger, Michael Stubert

    “…Current and next-generation communication infrastructures are enabling the realization of critical applications. These applications rely on operating systems…”
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  16. 16

    Approximation-aware Task Partitioning on an Approximate-Exact MPSoC (AxE) by Huemer, S., Baroughi, A. S., Shahhoseini, H. S., TaheriNejad, N.

    “…As the demand for increased performance and reduced energy consumption continues to grow, Quality of Service (QoS) adjustment approaches offer an effective way…”
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  17. 17

    Guidelines for Implementing Control Flow Checking into Automotive Embedded Applications Developed with C Language by Sini, Jacopo, Solouki, Mohammadreza Amel, Violante, Massimo

    “…Embedded systems, such as automotive applications, are increasingly used in safety-critical systems. The correct and reliable implementation of such systems…”
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  18. 18

    Performance Evaluation of PicoRV32 RISC-V Softcore for Resource-Constrained Devices by Jahnke, Marek, Bublitz, Lucas, Kulau, Ulf

    “…In this paper, an extensive analysis of the resource-efficient PicoRV32 softcore, which implements the RISC-V instruction set, is performed. The focus of the…”
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  19. 19

    Compensating Quadrature Hybrid Mismatch Effects in Integrated Balanced Power Amplifier by Rusanen, Jere, Shabanzadeh, Negar, Parssinen, Aarno, Rahkonen, Timo, Aikio, Janne P.

    “…This paper presents techniques to mitigate frequency dependent amplitude response of quadrature hybrid in an integrated quadrature balanced power amplifier…”
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  20. 20

    Transitioning to Chisel in University Education: Experiences and Lessons Learned by Pezzarossa, Luca, Schoeberl, Martin

    “…Hardware description languages are essential for specifying, designing, and verifying digital systems. VHDL and Verilog have been the predominant hardware…”
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