Search Results - "2021 25th International Symposium on VLSI Design and Test (VDAT)"

Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications by Pathak, Jay, Darji, Anand

“…In current CMOS technology for high-speed applications at the sub-14 nm technology node using In 0.53 Ga 0.47 As FinFETs is becoming a promising choice because…”
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Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation by Mythrai, Pragna, S, Kavitha, Singh, P., Shah, A. P., Vishwakarma, S. K., Reniwal, B. S.

“…In this work, for the first time, we have proposed and implemented the In-memory computation (IMC) of Hamming code for redundant bit generation(encoding) and…”
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Quantum Circuit Design of RECTANGLE Lightweight Cipher by Saravanan, P., Jenitha, J., Aasish, S. R., Sanjana, S.

“…Quantum computers will have a significant impact on the security aspects of many conventional cryptographic algorithms as the quantum circuit implementation of…”
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High Sensitivity and Power Efficient Heater Structure for Bulk Micromachined Thermal Accelerometer by Mukherjee, Rahul, Basu, Joydeep, Guha, Prasanta Kumar

“…In MEMS based thermal convective accelerometers, the structure of the constituent microheater plays a crucial role in determining the sensitivity of the…”
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Design and Implementation of Optimized Register File for Streaming Applications by Patan, Ayazulla Khan, Stathis, Dimitrios, Dhilleswararao, Pudi, Yang, Yu, Boppu, Srinivas, Hemani, Ahmed

“…The increased demand for energy-efficient solutions compels system architects to explore the opportunities for minimizing area and power in the critical parts…”
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Process Development for Very Deep Etching of Silicon Using Two Layer Masks for Fabrication of Mechanically Decoupled MEMS Gyroscope by Sharma, Deepak K., John, J, Supriya, G., Jambhalikar, Ashwini, Giridhar, M. S.

“…This work discusses the key issues associated with the process development for 200 μm thick structure for mechanically decoupled Silicon on Glass (SOG) MEMS…”
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Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis by Neeraj, Kaushal Kumari, Ranjan, Mohapatra Nihar

“…In this work, LDMOS transistors with different drift length and drift doping are characterized at cryogenic temperature. The physics behind the LDMOS…”
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A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment by Kolagatla, Venkata Reddy, J, Mervin, Darbar, Shabbir, Selvakumar, David, Saha, Sankha

“…This paper presents a randomized Montgomery Powering Ladder Modular Exponentiation (RMPLME) scheme for side channel attacks (SCA) resistant…”
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A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA by Krishnan, Abi K, Supriya, MH, Nalesh, S

“…Data acquisition systems are required to condition the low-level analog signals from various sensors and to convert them into digital format in order to…”
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Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links by Dev, S Sharon, Krishna, S M, Archana, S S, Kunthara, Rose George, Neethu, K, James, Rekha K

“…Network-on-Chip (NoC) has been a viable solution for resolving the complexities associated with inter-processor communications in a Chip Multi Processor (CMP)…”
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Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology by Reddy, K Lakshmi BhanuPrakash, Kumar, K.B Dheeraj, Pudi, Vikramkumar

“…In this paper, we have designed and proposed a novel D flip-flop using Carbon Nanotube Field-Effect Transistor (CNTFETs). The proposed flip-flop operates on a…”
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A Hardware Generator for Posit Arithmetic and its FPGA Prototyping by Shekhawat, Diksha, Jangir, Apoorva, Pandey, Jai Gopal

“…Posit arithmetic has better dynamic range and accuracy over the conventional IEEE-754 floating-point. In this paper, architectures for posit adder/subtractor…”
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An All-CMOS Supply, Temperature and Process Invariant Hybrid Current Reference For Power Efficient IoT Applications by Tapse, Soumya, Jandhyala, Srivatsava, Banti, Adithya Reddy

“…We propose an all-CMOS, supply independent, second-order temperature compensated, process invariant, 10.09 μA current reference circuit working on a 1.8 V…”
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A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation by Varun, TR, Nagulapalli, Rajasekhar, Raja, Immanuel

“…Conventional voltage mode Bandgap Reference (BGR) output is limited to 1.2V and hence is unsuitable for sub-1V operation in modern CMOS processes. The…”
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Comprehensive Study and Photovoltaic Performance Analysis of Eco-friendly Perovskite Solar Cell by Shubham, Pathak, Chetan, Pandey, Saurabh Kumar

“…In this study, we have investigated a non-toxic, lead-free perovskite solar cell that follows a planer organic-inorganic hybrid architecture and realized using…”
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Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design by Gupta, Yatin Kumar, Agrawal, Yash, Parekh, Rutu, Gohel, Bakul

“…Network-on-chip (NoC) has evolved as new paradigm for high-dense interconnect configurations in advanced integrated circuit designs. The increasing number of…”
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Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications by Sura, Ashish, Nehra, Vikas

“…The research on intrinsic spin of electrons results a new type of memory device, Spin-transfer-torque magnetic random access memory (STT-MRAM). The property of…”
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Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain by Yadav, Sarita, Chauhan, Nitanshu, Pandey, Archana, Pratap, Rajendra, Bulusu, Anand

“…The digital circuit design methodologies used conventionally consider the values of input capacitance (C in ) and parasitic (C p ) capacitance of an inverter…”
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Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing by Vohra, Sahibia Kaur, Thomas, Sherin, Sakare, Mahendra, Das, Devarshi Mrinal

“…The enhanced performance of neuromorphic computing over conventional Von Neumann computing results in high accuracy, energy and area efficient operations. The…”
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Formal Verification and Analysis of a Pseudo Random Number Generator by Selvakumar, David, Mervin, J, Pattanshetty, Shashikala, Vivian, D

“…Formal verification and analysis of a crypto hardware requires a formal specification, formal proof of equivalence of the specification with the hardware…”
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