Search Results - "2019 IEEE Latin American Test Symposium (LATS)"

A Reliability Analysis of a Deep Neural Network by Bosio, Alberto, Bernardi, Paolo, Ruospo, Annachiara, Sanchez, Ernesto

“…Deep Learning, and in particular its implementation using Convolutional Neural Networks (CNNs), is currently one of the most intensively and widely used…”
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Defect-Location Identification for Cell-Aware Test by Gao, Zhan, Malagi, Santosh, Marinissen, Erik Jan, Swenton, Joe, Huisken, Jos, Goossens, Kees

“…Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly reduces the amount of test escapes compared to conventional…”
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Use of ensemble methods for indirect test of RF circuits: can it bring benefits? by El Badawi, H., Azais, F., Bernard, S., Comte, M., Kerzerho, V., Lefevre, F.

“…Indirect testing of analog and RF integrated circuits is a widely studied approach, which has the benefits of relaxing requirements on test equipment and…”
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On the evaluation of SEU effects in GPGPUs by Du, B., Rodriguez Condia, Josie E., Sonza Reorda, M., Sterpone, L.

“…General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demand data applications which involve multi-signal, image and video…”
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Qubit-driven Fault Simulation by Hahanov, Vladimir, Gharibi, Wajeb, Litvinova, Eugenia, Chumachenko, Svetlana

“…Quantum data structures, methods, algorithms and software applications for parallel solution of combinatorial problems, including design and test, on classical…”
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MiFIT: A Fault Injection Tool to Validate the Reliability of Microprocessors by Aponte-Moreno, Alexander, Restrepo-Calle, Felipe, Pedraza, Cesar

“…Fault injection campaigns are a widely used method to validate the effectiveness of fault tolerance strategies, as well as to validate the reliability of…”
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Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches by Das, Abhishek, Touba, Nur A.

“…The number of marginal cells in static random-access memory (SRAM) increases as technology scales further. Spin transfer torque magnetic random-access memory…”
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Software-Based Mitigation for Memory Address Decoder Aging by Kraak, D.H.P., Gursoy, C.C., Agbo, I.O., Taouil, M., Jenihhin, M., Raik, J., Hamdioui, S.

“…Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary…”
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Analyzing graph-based algorithms employed to generate test cases from finite state machines by Mariano, Matheus Monteiro, Souza, Erica F., Endo, Andre T., Vijaykumar, Nandamudi L.

“…Context: Model-Based Testing (MBT) is a technique that employs formal models to represent reactive systems' behav-ior and generates test cases. Such systems…”
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Low latency reconfiguration mechanism for fine-grained processor internal functional units by Ferreira, Raphael Segabinazzi, Nolte, Jorg

“…The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out…”
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Comparing Exhaustive and Random Fault Injection Methods for Configuration Memory on SRAM-based FPGAs by Benevenuti, Fabio, Kastensmidt, Fernanda Lima

“…In this paper, authors propose two approaches of fault injection emulation performed in the configuration memory bits of an SRAM-based FPGA. One is based on…”
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Microservices-based architecture for fault diagnosis in tele-rehabilitation equipment operated via Internet by Alvarez Q., Juan M., Sanabria O., John A., Garcia M., Jose I

“…This paper presents the design of a microservices based architecture allows early fault detection and diagnosis on a remote controlled physical rehabilitation…”
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Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems by Lojda, Jakub, Podivinsky, Jakub, Kotasek, Zdenek

“…As electronic systems penetrate into areas in which reliable computing is required, new methods incorporating reliability into these systems arise. It is…”
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Mixed-level identification of fault redundancy in microprocessors by Oyeniran, Adeboye Stephen, Ubar, Raimund, Jenihhin, Maksim, Gursoy, Cemil Cem, Raik, Jaan

“…A new high-level implementation independent functional fault model for control faults in microprocessors is introduced. The fault model is based on the…”
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A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs by Alvarez-Fontecilla, Enrique, Abusleme, Angel

“…The linearity of charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) is affected by systematic mismatch in its…”
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A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites by Rigo, Cezar A., Luza, Lucas M., Tramontin, Elder D., Martins, Victor, Martinez, Sara Vega, Slongo, Leonardo K., Seman, Laio O., Dilillo, Luigi, Vargas, Fabian L., Bezerra, Eduardo A.

“…This work presents a fault-tolerant reconfigurable hardware platform for the communication module of satellites. A printed circuit board (PCB) was designed…”
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A Flexible UVM-Based Verification Framework Reusable with Avalon, AHB, AXI and Wishbone Bus Interfaces for an AES Encryption Module by Plasencia-Balabarca, Frank, Mitacc-Meza, Edward, Raffo-Jara, Mario, Silva-Cardenas, Carlos

“…The fast and continuous development of digital circuits lead to complex and unpredictable designs which have to be submitted under high-standard verification…”
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Softerror mitigation for multi-core processors based on thread replication by Serrano-Cases, Alejandro, Restrepo-Calle, Felipe, Cuenca-Asensi, Sergio, Martinez-Alvarez, Antonio

“…This paper presents a technique to mitigate faults induced by radiation in standalone embedded systems based on multi-core processors. To achieve this goal,…”
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Probabilistic High-Level Estimation of Vulnerability and Fault Mitigation of Critical Systems Using Fault-Mitigation Trees (FMTs) by Ammar, Marwan, Hamad, Ghaith Bany, Ait Mohamed, Otmane

“…The development of safety-critical systems is a rather challenging task, especially due to the cost and complexity associated with this endeavor. For this…”
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A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture by Lara, Estevan, Debon, Guilherme, Goerl, Roger, Villa, Paulo, Schramm, Dorian, Poehls, Leticia B., Vargas, Fabian

“…The use of multicore processors in general-purpose real-time embedded systems has experienced a huge increase in recent years. Unfortunately, critical…”
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