Search Results - "2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)"

In search of a hole inversion layer in \mathrm/\mathrm/\mathrm diodes through I- V characterization using dedicated ring-shaped test structures by Gupta, Gaurav, Thammaiah, Shivakumar D., Hueting, Raymond J. E., Nanver, Lis K.

“…Palladium (Pd) capped molybdenum-oxide (MoO x ) thin films deposited bye-beam evaporation on p- and n-type silicon (Si) substrates were investigated employing…”
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Comparison of MOSFET Threshold Voltage Extraction Methods with Temperature Variation by Cheng, Yu-Hsing

“…Threshold voltage is a fundamental parameter for MOSFET device and technology characterization. Multiple threshold voltage extraction methods are compared in…”
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Proposed one-dimensional passive array test circuit for parallel kelvin measurement with efficient area use by Rerecich, Matthew, Young, Chadwin D.

“…A test structure and measurement method are proposed that permits measurement of several resistors in parallel using a kelvin method with only two independent…”
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Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation by Islam, A.K.M. Mahfuzul, Shimizu, Ryota, Onodera, Hidetoshi

“…We present measurement results of the effect of switching speed and logic depth on random telegraph noise (RTN) induced delay fluctuation using a test chip…”
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Two-transistor Voltage-Measurement-Based Test Structure for Fast Extraction of MOS Mismatch Design Parameters by Brito, Juan Pablo Martinez, Bampi, Sergio

“…This paper proposes a new test structure and a measurement method for measuring MOS transistors mismatches. The structure is based on the combination of two…”
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Chairman's Letter

“…Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the…”
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Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials by Maeda, Takeru, Omura, Yuya, Teramoto, Akinobu, Kuroda, Rihito, Suwa, Tomoyuki, Sugawa, Shigetoshi

“…A newly developed resistance measurement platform is presented in this paper. The measurement platform consists of an array test circuit fabricated by a…”
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Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges by Couret, Marine, Fischer, Gerhard, Fregonese, Sebastien, Zimmer, Thomas, Maneux, Cristell

“…A thermal impedance model of single-finger and multi-finger SiGe heterojunction bipolar transistors (HBTs) is presented. The heat flow analysis through the…”
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Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions by Jaoul, Mathieu, Ney, David, Celi, Didier, Maneux, Cristell, Zimmer, Thomas

“…This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions…”
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A compact model of I -V characteristic degradation for organic thin film transistors by Saito, Michiaki, Shintani, Michihiro, Kuribara, Kazunori, Ogasahara, Yasuhiro, Sato, Takashi

“…The lifetime of organic thin film transistors is known to be significantly shorter than that of silicon MOSFETs. It is hence important to predict their…”
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Wafer-Level Test Solution Development for a Quad-Channel Linear Driver Die in a 400G Silicon Photonics Transceiver Module by Wang, Ye, Ding, Hanyi, Blakely, Barry, Yan, Aidong

“…In this paper, we demonstrate a wafer-level sorting test solution developed for quad-channel linear driver to be used in a 400G silicon photonics transceiver…”
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Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive ring Oscillators by Kishida, Ryo, Asuke, Takuya, Furuta, Jun, Kobayashil, Kazutoshi

“…Measuring bias temperature instability (BTI) by ring oscillators (ROs) is frequently used. However, the performance of a semiconductor chip is fluctuated…”
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Taming Emerging Devices' Variation and Reliability Challenges with Architectural and System Solutions [Invited] by Wang, Yuyang, Shao, Leilai, Lastras-Montano, Miguel Angel, Cheng, Kwang-Ting

“…Emerging devices are promising alternatives to traditional CMOS technologies as proposed in various solutions for future computation and communication systems…”
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Test Structures for Characterising the Silver Chlorination Process During Integrated Ag/AgCl Reference Electrode Fabrication by Dunare, C., Marland, J.R.K., Blair, E.O., Tsiamis, A., Moorel, F., Terry, J.G., Walton, A.J., Smith, S.

“…Robust and repeatable processes are required to fabricate reference electrodes for micro-scale integrated electrochemical sensors. One method for this is to…”
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A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies by Higo, Akio, Sawamura, Tomoki, Fujiwara, Makoto, Ota, Etsuko, Mizushima, Ayako, Lebrasseur, Eric, Arakawa, Taro, Mita, Yoshio

“…High-throughput electron beam (EB) lithography technologies such as variable shape beam (VSB) and character projection (CP) are drawing much interests to the…”
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On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch by Jain, Poorvi, Das, Bishnu Prased

“…In this work, an all-digital on-chip threshold voltage variability detector is proposed to detect the local random threshold voltage variation from an array of…”
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Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips by Hess, Christopher, Brozek, Tomasz, Schneider, Hendrik, Yu, Yuan, Lunenborg, Meindert, Ng, Khim Hong, Ciplickas, Dennis, Vallishayee, Rakesh, Dolainsky, Christoph, Weiland, Larg H.

“…More and more non volatile memory bit cell candidates are emerging which can be implemented between two metal layers in the BEOL process. Thus, short flow…”
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Experimental Extraction of Body Bias Dependence of Low Frequency Noise in sub-micron MOSFETs from Subthreshold to Moderate Inversion Regime by Tanaka, Chika, Adachi, Kanna, Nakayama, Atsushi, Iguchi, Yasuhiko, Yoshitomi, Sadayuki

“…In this study, we investigate low frequency noise under the reverse body bias conditions from subthreshold to moderate inversion regime with 1/f noise…”
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Probing impact on pad moisture tightness: A challenge for pad size reduction by Vidal-Dho, Matthias, Hubert, Quentin, Gonon, Patrice, Delorme, Philippe, Jacquot, Jonathan, Marchetti, Maxime, Beauvisage, Ludovic, Moragues, Jean-Michel, Potard, Pascale, Fornara, Pascal, Escales, Jean-Philippe, Sallagoity, Pascal, Pizzuto, Olivier, Maury, Delphine, Mirabel, Jean-Michel

“…This paper underlines the damages induced by probing on narrow pads reliability of specifically designed test structures placed on dicing streets and indicates…”
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Analysis of Test Structure Design Induced Variation in on Si On-wafer TRL Calibration in sub-THz by Yadav, Chandan, Fregonese, Sebastien, Deng, Marina, Cabbia, Marco, De Matos, Magali, Jaoul, Mathieu, Zimmer, Thomas

“…In this paper, we present on-wafer S-parameter measurement of test structures designed and fabricated on silicon substrate for transistor de-embedding upto 220…”
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