Search Results - "2017 International Conference of Microelectronic Test Structures (ICMTS)"

Input capacitance determination of power MOSFETs from switching trajectories by Oishi, Kazuki, Shintani, Michihiro, Hiromoto, Masayuki, Sato, Takashi

“…A novel method for determining input capacitance of power MOSFETs is proposed. Through measurements of gate charge transfer trajectories during switching,…”
Get full text

Detailed characterization and critical discussion of series resistance in graphene-metal contacts by Venica, Stefano, Driussi, Francesco, Gahoi, Amit, Passi, Vikram, Palestri, Pierpaolo, Lemme, Max C., Selmi, Luca

“…We apply the contact-end resistance method to TLM structures in order to characterize the graphene-metal contact resistance. A critical analysis of the…”
Get full text

Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs by Bucher, Matthias, Nikolaou, Aristeidis, Mavredakis, Nikolaos, Makris, Nikolaos, Coustans, Mathieu, Lolivier, Jerome, Habas, Predrag, Acovic, Alexandre, Meyer, Rene

“…Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper,…”
Get full text

Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI by Pradeep, Krishna, Gouget, Gilles, Poiroux, Thierry, Scheer, Patrick, Juge, Andre, Ghibaudo, Gerard

“…In this work, robust methodologies for parameter extraction using split C-V measurements in FD-SOI structures are developed. These methods enable an automated…”
Get full text

Measurement of mismatch factor and noise of SRAM PUF using small bias voltage by Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, Shinohara, Hirofumi

“…Mismatch factor of SRAM bit cell and noise factor that affects its power up state are measured using 256 bit SRAM PUF test structure with bias voltage inputs…”
Get full text

Test structures for optimizing polymer electrolyte performance in a microfabricated electrochemical oxygen sensor by Marland, J. R. K., Dunare, C., Tsiamis, A., Gonzalez-Fernandez, E., Blair, E. O., Smith, S., Terry, J. G., Murray, A. F., Walton, A. J.

“…Test structures were produced for optimizing the design and fabrication of a patterned solid polymer electrolyte in an electrochemical oxygen sensor…”
Get full text

A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators by Mahfuzul Islam, A. K. M., Nakai, Tatsuya, Onodera, Hidetoshi

“…This paper proposes a statistical modeling methodology of RTN (Random Telegraph Noise) gate size dependency utilizing skewed ring oscillator (RO) structures…”
Get full text

Test structures for the characterisation of sensor packaging technology by Blair, E. O., Buchoux, A., Tsiamis, A., Dunare, C., Marland, J. R. K., Terry, J. G., Smith, S., Walton, A. J.

“…This paper presents three test structures targeted at characterising sensor packaging materials for liquid environments. The test structures enable the…”
Get full text

Statistical characterization and modeling of drain current local and global variability in 14 nm bulk FinFETs by Karatsori, T., Theodorou, C., Lavieville, R., Chiarella, T., Mitard, J., Horiguchi, N., Dimitriadis, C. A., Ghibaudo, G.

“…A detailed statistical characterization and modeling of drain current local and global variability in 14nm Si bulk FinFET devices is performed. To this end, an…”
Get full text

A microsecond time resolved current collapse test setup dedicated to GaN-based Schottky diode characterization by Lorin, T., Van Den Daele, W., Gillot, C., Charles, M., Biscarrat, J., Plissonnier, M., Ghibaudo, G., Reimbold, G.

“…This paper presents a test setup to characterize current collapse effects in power diodes such as GaN-based Schottky junctions. The setup principle and its…”
Get full text

Dealing with leakage current in TLM and CTLM structures with vertical junction isolation by Bystrova, Svetlana N., Smits, Sander M., Klootwijk, Johan H., Wolters, Rob A. M., Kovalgin, Alexey Y., Nanver, Lis K., Schmitz, Jurriaan

“…Transmission line method (TLM) structures are often employed to extract contact resistivity between a metal and a doped semiconductor region. In this article…”
Get full text

Design of a Broadband CMOS RF Power Amplifier to establish device-circuit aging correlations by Barajas, E., Mateo, D., Aragones, X., Crespo-Yepes, A., Rodriguez, R., Martin-Martinez, J., Nafria, M.

“…This paper presents the design of a Broadband CMOS RF Power Amplifier, suitable to be stressed at circuit level but with the possibility to be measured both at…”
Get full text

A new test vehicle for RRAM array characterization by Nguyen, C., Cagli, C., Kadura, L., Nodin, J.-F, Bernasconi, S., Reimbold, G.

“…In this paper we present a new test vehicle designed for Resistive Random Access Memories (RRAM) arrays (from single bit to 1Mbits) characterization. The…”
Get full text

Vth-shiftable SRAM cell TEGs for direct measurement for the immunity of the threshold voltage variability by Yamaguchi, Shogo, Imi, Hitoshi, Tokumaru, Shogo, Kondo, Takahiro, Yamamoto, Hiromasa, Nakamura, Kazuyuki

“…We developed VTSTs for 6T-SRAM and RL-SRAM and evaluated them to investigate the influences of SRAM operation by Vth fluctuation using measured FCMs and…”
Get full text

A variability-based analysis technique revealing physical mechanisms of MOSFET low-frequency noise by Both, Thiago H., Croon, Jeroen A., Banaszeski da Silva, Mauricio, Tuinhout, Hans P., Zegers-van Duijnhoven, Adrie, Scholten, Andries J., Wirth, Gilson I.

“…This paper presents a technique for statistical analysis of MOSFET low-frequency noise (LFN) based on the autocorrelation coefficient of numerous LFN power…”
Get full text

Test structures for understanding the impact of ultra-high vacuum metal deposition on top-gate MoS2 field-effect-transistors by Bolshakov, Pavel, Peng Zhao, Smyth, Christopher M., Azcatl, Angelica, Wallace, Robert M., Young, Chadwin D., Hurley, Paul K.

“…Greek crosses and TLM test structures were fabricated and characterized along with top-gate field effect transistors. We also show the usefulness and…”
Get full text

Development of an Advanced System for Automated 200 mm Wafer Mapping of Stress Using Test Structures by Lokhandwala, S., Murray, J., Smith, S., Mount, A. R., Terry, J. G., Walton, A. J.

“…Controlling and understanding the stress in materials is of major importance in the successful fabrication of MEMS devices. Failure to properly account for…”
Get full text

An arrayed test structure for transistor damage assessment induced by circuit analysis and repairing processes with back-side-accessing Focused Ion Beam by Usami, Naoto, Kinoshita, Jun, Ikeno, Rimon, Okamoto, Yuki, Tanno, Masaaki, Asada, Kunihiro, Mita, Yoshio

“…We propose an arrayed test structure to assess the damages of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed under back-side LSI…”
Get full text

Impact of access resistance on New-Y function methodology for MOSFET parameter extraction in advanced FD-SOI technology by Henry, Jean-Baptiste, Cros, Antoine, Rosa, Julien, Rafhay, Quentin, Ghibaudo, Gerard

“…In this work, an upgraded version of the so called New Y function MOSFET parameter extraction methodology is proposed, taking the impact of access resistance…”
Get full text

True Kelvin CMOS Test Structure to achieve accurate and repeatable DC wafer-level measurements for device modelling applications by Choon Beng Sia

“…A 6-pad True Kelvin Test Structure for advanced CMOS devices is proposed in this work. It allows test engineers to make very accurate and repeatable…”
Get full text