Search Results - "2016 International Conference on Field-Programmable Technology (FPT)"

Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC by Nurvitadhi, Eriko, Sheffield, David, Jaewoong Sim, Mishra, Asit, Venkatesh, Ganesh, Marr, Debbie

“…Deep neural networks (DNNs) are widely used in data analytics, since they deliver state-of-the-art accuracies. Binarized neural networks (BNNs) are recently…”
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Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks by DiCecco, Roberto, Lacey, Griffin, Vasiljevic, Jasmina, Chow, Paul, Taylor, Graham, Areibi, Shawki

“…Convolutional Neural Networks (CNNs) have gained significant traction in the field of machine learning, particularly due to their high accuracy in visual…”
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Spector: An OpenCL FPGA benchmark suite by Gautier, Quentin, Althoff, Alric, Pingfan Meng, Kastner, Ryan

“…High-level synthesis tools allow programmers to use OpenCL to create FPGA designs. Unfortunately, these tools have a complex compilation process that can take…”
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A memory-based realization of a binarized deep convolutional neural network by Nakahara, Hiroki, Yonekawa, Haruyoshi, Sasao, Tsutomu, Iwamoto, Hisashi, Motomura, Masato

“…A pre-trained deep convolutional neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires high…”
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Automatic code generation of convolutional neural networks in FPGA implementation by Zhiqiang Liu, Yong Dou, Jingfei Jiang, Jinwei Xu

“…Convolutional neural networks (CNNs) have gained great success in various computer vision applications. However, state-of-the-art CNN models are…”
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Hardware TCP Offload Engine based on 10-Gbps Ethernet for low-latency network communication by Li Ding, Ping Kang, Wenbo Yin, Linli Wang

“…This paper introduces a hardware TCP Offload Engine (TOE) aiming at low-latency communication systems. The throughput can reach 9.99 Gbps with the Jumbo frame…”
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An efficient implementation of online arithmetic by Yiren Zhao, Wickerson, John, Constantinides, George A.

“…We propose the first hardware implementation of standard arithmetic operators - addition, multiplication, and division - that utilises constant compute…”
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Network-attached FPGAs for data center applications by Weerasinghe, Jagath, Polig, Raphael, Abel, Francois, Hagleitner, Christoph

“…FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They are used as accelerators to boost the compute power of individual…”
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FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs by Echavarria, Jorge, Wildermann, Stefan, Becher, Andreas, Teich, Jurgen, Ziener, Daniel

“…During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power…”
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An acceleration of a random forest classification using Altera SDK for OpenCL by Nakahara, Hiroki, Jinguji, Akira, Fujii, Tomonori, Sato, Simpei

“…A random forest (RF) is a kind of ensemble machine learning algorithm used for a classification and a regression. It consists of multiple decision trees that…”
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Hypervisor mechanisms to manage FPGA reconfigurable accelerators by Tian Xia, Prevotet, Jean-Christophe, Nouvel, Fabienne

“…In the last decade, the research on CPU-FPGA hybrid architectures has become a hot topic. One of the main challenges in this domain consists in efficiently and…”
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Time-independent discrete Gaussian sampling for post-quantum cryptography by Khalid, A., Howe, J., Rafferty, C., O'Neill, M.

“…As the development of a viable quantum computer nears, existing widely used public-key cryptosystems, such as RSA, will no longer be secure. Thus, significant…”
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Analysis of transient voltage fluctuations in FPGAs by Gnad, Dennis R. E., Oboril, Fabian, Kiamehr, Saman, Tahoori, Mehdi B.

“…Due to recent technology scaling trends and increased circuit complexity, process and runtime variabilities are becoming major threats for correct circuit…”
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High-speed regular expression matching with pipelined automata by Matousek, Denis, Korenek, Jan, Pus, Viktor

“…Pattern matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links, pattern matching…”
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High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs by Tatsumura, Kosuke, Yazdanshenas, Sadegh, Betz, Vaughn

“…Many important applications demand large amounts of on-chip memory both to fully utilize an FPGA's computational capacity and to minimize energy-consuming…”
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Fine-grained module-based error recovery in FPGA-based TMR systems by Zhuoran Zhao, Agiakatsikas, Dimitris, Nguyen, Nguyen T. H., Cetin, Ediz, Diessel, Oliver

“…Space processing applications deployed on SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs)…”
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An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating by He Qi, Ayorinde, Oluseyi, Calhoun, Benton H.

“…The rapid development of the Internet-of-Things requires hardware that is both low-energy and flexible, and a near/sub-threshold FPGA is a very promising…”
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Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs by Pinilla, Jose P., Wilton, Steven J. E.

“…High-Level Synthesis (HLS) has emerged as a leading technology to reduce the design time and complexity that is associated with reconfigurable systems. In…”
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Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs by Asghar, Ali, Iqbal, Muhammad Mazher, Ahmed, Waqar, Ali, Mujahid, Parvez, Husain, Rashid, Muhammad

“…In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean…”
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FPGA-based acceleration of FDAS module using OpenCL by Haomiao Wang, Ming Zhang, Thiagaraj, Prabu, Sinnen, Oliver

“…The Square Kilometre Array (SKA) project will be the world largest radio telescope array. With the growth of the number of antennas, the signals that need to…”
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