Search Results - "2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)"

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  1. 1

    Robust smartphone-based human activity recognition using a tri-axial accelerometer by Torres-Huitzil, Cesar, Nuno-Maganda, Marco

    “…Mobile artifacts such as smartphones have made possible the development of wearable systems for user activity monitoring and recognition due to the synergy of…”
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    Conference Proceeding
  2. 2

    Optimal location and sizing of Distributed Generators using a hybrid methodology and considering different technologies by Grisales, L. F., Grajales, A., Montoya, O. D., Hincapie, R. A., Granada, M.

    “…In this article, a hybrid methodology for selecting and location of Distributed Generators (DG) in distribution systems is presented. The mathematical model…”
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  3. 3

    Evaluating SEU fault-injection on parallel applications implemented on multicore processors by Vargas, Vanessa, Ramos, Pablo, Velazco, Raoul, Mehaut, Jean-Francois, Zergainoh, Nacer-Eddine

    “…The widespread use of multicore processors in computing systems and the imperative necessity of exploiting massive parallelism to improve performance and…”
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  4. 4

    Towards reversible QCA computers: Reversible gates and ALU by Chaves, Jeferson F., Silva, Douglas S., Camargos, Victor V., Vilela Neto, Omar P.

    “…This work presents a novel implementation of reversible gates and reversible ALU, all based in quantum-dot cellular automata (QCA). QCA has been considered as…”
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  5. 5

    BAT-Hermes: A transition-signaling bundled-data NoC router by Gibiluka, Matheus, Moreira, Matheus Trevisan, Moraes, Fernando Gehm, Vilar Calazans, Ney Laert

    “…Networks on chip (NoCs) are efficient infrastructures to enable communication among the large number of IPs that compose modern systems on chip (SoCs)…”
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  6. 6

    Automated RDSon characterization for power MOSFETS by Escalona-Cruz, Pedro J., Jimenez-Cedeno, Manuel A., Palomera-Garcia, Rogelio

    “…This paper presents an automated R DSon characterization test for Power MOSFETS. Considerations for both hardware and software development, and integration…”
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  7. 7

    FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage by Lopez, Giorgio, Napoli, Ettore, Strollo, Antonio G. M.

    “…Multispectral and Hyperspectral Images are wide-spread in Remote Sensing and Space Imaging Applications: they are typically three dimensional arrays of images…”
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  8. 8

    An RRAM-based Oscillatory Neural Network by Jackson, Thomas C., Sharma, Abhishek A., Bain, James A., Weldon, Jeffrey A., Pileggi, Lawrence

    “…Oscillatory Neural Networks (ONNs) are an intriguing brain-inspired paradigm for massively parallel computing, but implementations in CMOS fail to produce…”
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  9. 9

    S-GMOF: A gradient-based complexity reduction algorithm for depth-maps intra prediction on 3D-HEVC by Sanchez, Gustavo, Saldanha, Mario, Zatt, Bruno, Porto, Marcelo, Agostini, Luciano

    “…This paper proposes a complexity reduction algorithm for the depth maps intra prediction of the emerging 3D High Efficiency Video Coding (3D-HEVC). The…”
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  10. 10

    On the functional test of the cache coherency logic in multi-core systems by Perez Acle, J., Cantoro, R., Sanchez, E., Sonza Reorda, M.

    “…Multi-core systems are becoming particularly common, due to the high performance they can deliver. Their performance strongly depends on the availability of…”
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    Conference Proceeding
  11. 11

    Resistorless switched-capacitor current reference based on the MOSFET ZTC condition by Toledo, Pedro, Klimach, Hamilton, Cordova, David, Bampi, Sergio, Fabris, Eric

    “…The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and…”
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  12. 12

    S-plane bode plots - identifying poles and zeros in a circuit transfer function by Hashemian, Reza

    “…A simple s-plane transformation scheme is introduced for analog circuits. Here the jω axis is moved step by step along the σ axis to meet the poles and zeros…”
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  13. 13

    Techniques for square ELT simulation: A comparative study by Ilha Vaz, Pablo, Wiltgen Junior, Alberto, Inacio Wirth, Gilson

    “…This work aims to study different analytical and numerical models to estimate effective W/L ratio considering transistors with enclosed gate geometry, suitable…”
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  14. 14

    A fast pruning technique for low-power inexact Circuit design by Broc, Johan, Gaillardon, Pierre-Emmanuel, Amaru, Luca, Murillo, Jaume Joven, Palem, Krishna, De Micheli, Giovanni

    “…Inexact Circuits are circuits in which the accuracy of the output can be traded for cost savings (energy, area and/or delay). In the context of advanced…”
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  15. 15

    Multimode 2.4 GHz CMOS power amplifier with gain control for efficiency enhancement at power backoff by Santos, E. L., Leite, B., Mariano, A.

    “…In this paper, a power amplifier (PA) with gain control is presented for 2.4 GHz applications. The power gain can be digitally controlled in six steps by the…”
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  16. 16

    Partial triplication of a SPARC-V8 microprocessor using fault injection by Bottoni, Cyril, Coeffic, Benjamin, Daveau, Jean-Marc, Naviner, Lirida, Roche, Philippe

    “…We present in this paper the application of fault injection to selective hardening by triplication of a pipelined SPARC-V8 microprocessor. Fault injection is…”
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  17. 17

    Signal enhancement for gunshot DOA estimation with median filters by Borzino, A. M. C. R., Apolinario, J. A., de Campos, M. L. R., Biscainho, L. W. P.

    “…The estimation of the direction of arrival (DOA) of gunshot sounds when the distance between firing and recording sites becomes large, as in a sniper scenario,…”
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  18. 18

    Threshold voltage extraction circuit for low voltage CMOS design using basic long-channel MOSFET by Toledo, Luis Eduardo, Petrashin, Pablo Antonio, Lancioni, Walter Jose, Vazquez, Carlos Daniel

    “…The threshold voltage (V th ) is a key parameter in MOSFET design and modeling. There are many definitions and extraction methods, each one given with a focus…”
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  19. 19

    TSV protection: Towards secure 3D-MPSoC by Sepulveda, Johanna, Gogniat, Guy, Florez, Daniel, Diguet, Jean-Philippe, Pires, Ricardo, Strum, Marius

    “…Through-Silicon-Vias (TSVs) are the key enabling technology for high performance of three-dimension Multi-processor System-on-Chip (3D-MPSoC). Physical…”
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  20. 20

    Realization of 4D ladder structured digital filters by Kousoulis, M. T., Antoniou, G. E.

    “…This paper introduces generalized circuit and state-space realizations for four-dimensional (4D) ladder structured filters. The proposed 4D circuit realization…”
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