Search Results - "2014 IEEE 20th International On-Line Testing Symposium (IOLTS)"

A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans by Dupuis, Sophie, Ba, Papa-Sidi, Di Natale, Giorgio, Flottes, Marie-Lise, Rouzeyre, Bruno

“…Hardware piracy is a threat that is becoming more and more serious these last years. The different types of threats include mask theft, illegal overproduction,…”
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Double node charge sharing SEU tolerant latch design by Katsarou, Katerina, Tsiatouhas, Yiorgos

“…Single event upsets (SEUs) that affect adjacent nodes in a design, by charge sharing mechanisms among these nodes, are a great concern in nanometer SRAMs,…”
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A novel methodology to increase fault tolerance in autonomous FPGA-based systems by Di Carlo, Stefano, Gambardella, Giulio, Prinetto, Paolo, Rolfo, Daniele, Trotta, Pascal, Vallero, Alessandro

“…Nowadays Field-Programmable Gate Arrays (FP-GAs) are increasingly used in critical applications. In these scenarios fault tolerance techniques are needed to…”
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Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs by Desogus, Marco, Sterpone, Luca, Codinachs, David Merodio

“…Predicting soft errors on SRAM-based FPGAs without a wasteful time-consuming or a high-cost has always been a very difficult goal. Among the available methods,…”
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Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis by Kumar, Raghavan, Jovanovic, Philipp, Polian, Ilia

“…State-of-the-art fault-based cryptanalysis methods are capable of breaking most recent ciphers after only a few fault injections. However, they require…”
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Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches by Yalcin, Gulay, Islek, Emrah, Tozlu, Oyku, Reviriego, Pedro, Cristal, Adrian, Unsal, Osman S., Ergin, Oguz

“…Scaling supply voltage to near-threshold is a very effective approach in reducing the energy consumption of computer systems. However, executing below the safe…”
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Multivariate outlier modeling for capturing customer returns - How simple it can be by Tikkanen, Jeff, Sumikawa, Nik, Wang, Li-C, Abadir, Magdy S.

“…Univariate outlier analysis has become a popular approach for improving quality. When a customer return occurs, multivariate outlier analysis extends the…”
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Online error detection and recovery in dataflow execution by Alves, Tiago A. O., Kundu, Sandip, Marzulo, Leandro A. J., Franca, Felipe M. G.

“…The processor industry is well on its way towards manycore processors that comprise of large number of simple cores. The shift towards multi and manycores…”
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Versatile architecture-level fault injection framework for reliability evaluation: A first report by Foutris, Nikos, Kaliorakis, Manolis, Tselonis, Sotiris, Gizopoulos, Dimitris

“…Forthcoming technologies hold the promise of a significant increase in integration density, performance and functionality. However, a dramatic change in…”
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A placement strategy for reducing the effects of multiple faults in digital circuits by Pagliarini, Samuel N., Pradhan, Dhiraj

“…This paper proposes a fault-aware placement strategy for digital circuits. Placement algorithms usually have a goal of reducing the overall chip area and…”
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New approaches for synthesis of redundant combinatorial logic for selective fault tolerance by Hao Xie, Li Chen, Rui Liu, Evans, Adrian, Alexandrescu, Dan, Shi-Jie Wen, Wong, Rick

“…With shrinking process technologies, the likelihood of mid-life faults in combinatorial logic is increasing. Approximate logic functions are a promising…”
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Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors by Badack, Christian, Kern, Thomas, Gössel, Michael

“…In this paper we propose a modification of double error correcting (DEC) BCH codes that allows for a fast correction of arbitrary 1-bit and 2-bit errors, as…”
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Error masking with approximate logic circuits using dynamic probability estimations by Sanchez-Clemente, A., Entrena, L., Garcia-Valderas, M.

“…Approximate logic circuits can be used in hardware redundancy approaches to reduce the overheads at the expense of slightly sacrificing robustness. However, a…”
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Framework for economical error recovery in embedded cores by Upasani, Gaurang, Vera, Xavier, Gonzalez, Antonio

“…The vulnerability of the current and future processors towards transient errors caused by particle strikes is expected to increase rapidly because of…”
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Two complementary approaches for studying the effects of SEUs on HDL-based designs by Mansour, W., Aguirre, M. A., Guzman-Miranda, H., Barrientos, J., Velazco, R.

“…In this paper, a comparison between two HDL-based fault-injection methods, FT-UNSHADES and NETFI, is presented. Fault-injection campaigns were performed on a…”
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Power-aware optimization of software-based self-test for L1 caches in microprocessors by Theodorou, G., Kranitis, N., Paschalis, A., Gizopoulos, D.

“…In the era of terascale integration, the "reliability wall" and the "power wall" arise as barriers imposing significant challenges to the microprocessor…”
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Timing for virtual TMR in logic circuits by Müller, Sebastian, Koal, Tobias, Schölzel, Mario, Vierhaus, Heinrich T.

“…Digital integrated circuits fabricated in nano-technologies have first shown to be more vulnerable to transient errors effects than their predecessors. But…”
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Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687 by Petersen, Kim, Nikolov, Dimitar, Ingelsson, Urban, Carlsson, Gunnar, Zadegan, Farrokh Ghani, Larsson, Erik

“…As fault handling in multi-processor system-on-chips (MPSoCs) is a major challenge, we have developed an MPSoC demonstrator that enables experimentation on…”
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From an analytic NBTI device model to reliability assessment of complex digital circuits by Aryan, N. Pour, Listl, A., Heiss, L., Yilmaz, C., Georgakos, G., Schmitt-Landsiedel, D.

“…In safety critical applications precise characterization of circuits to predict the lifetime reliability is a key challenge. This paper proposes a reliability…”
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Area-efficient synthesis of fault-secure NoC switches by Dalirsani, Atefe, Kochte, Michael A., Wunderlich, Hans-Joachim

“…This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational…”
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