Search Results - "2013 Symposium on VLSI Circuits"

A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS by Elhadidy, Osama, Palermo, Samuel

“…A serial I/O receiver efficiently implements a decision feedback equalizer (DFE) employing 2 IIR taps for improved long-tail ISI cancellation. The use of a…”
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A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS by Belfanti, Sandro, Roth, Christoph, Gautschi, Michael, Benkeser, Christian, Qiuting Huang

“…This paper presents a turbo-decoder ASIC for 3GPP LTE-Advanced supporting all specified code rates and block sizes. The highly parallelized architecture…”
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An integrated pulse wave velocity sensor using Bio-impedance and noise-shaped body channel communication by Woojae Lee, SeongHwan Cho

“…In this paper, an integrated pulse wave velocity (PWV) sensor that adapts ECG and Bio-impedance (BI) method is proposed. PWV is calculated by measuring the…”
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A 28.6µW mixed-signal processor for epileptic seizure detection by Tsan-Jieh Chen, Sheng-Cheng Lee, Chia-Hsiang Yang, Chin-Fong Chiu, Herming Chiueh

“…An energy-efficient epileptic seizure detection system-on-chip (SoC) is integrated in 10.41mm 2 in 0.18μm CMOS. The chip integrates analog frontend, a 16-bit…”
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First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects by Mitard, J., Witters, L., Vincent, B., Franco, J., Favia, P., Hikavyy, A., Eneman, G., Loo, R., Brunco, D. P., Kabir, N., Bender, H., Sebaai, F., Vos, R., Mertens, P., Milenin, A., Vecchio, E., Ragnarsson, L.-A, Collaert, N., Thean, A.

“…Highly-strained Ge-in-STI pFETs on SiGe55% SRBs are demonstrated with mobilities up to 550 cm 2 /Vs and record NBTI reliability at T INV ~1.7 nm. Short channel…”
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A 288fs RMS jitter versatile 8-12.4GHz wide-band Fractional-N synthesizer for SONET and SerDes communication standards in 40nm CMOS by Ahmadi, Mahmoud Reza, Pi, Dave, Catli, Burak, Singh, Ullas, Bo Zhang, Zhi Huang, Momtaz, Afshin, Jun Cao

“…This paper presents a wide-band analog Fractional-N clock synthesizer operating from 8 to 12.4GHz suited for data communication standards. The synthesizer…”
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An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI by Chen, Vanessa H.-C, Pileggi, Lawrence

“…This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset…”
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A 9b, 1.12ps resolution 2.5b/stage pipelined time-to-digital converter in 65nm CMOS using time-register by KwangSeok Kim, WonSik Yu, SeongHwan Cho

“…This paper presents a 2.5b/stage pipelined time-to-digital converter (TDC). For pipelined operation, a novel time-register is proposed which is capable of…”
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A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS by Sachin Rao, Reddy, Karthikeyan, Young, Brian, Hanumolu, Pavan Kumar

“…A deterministic digital background calibration technique to correct non-linearity in VCO-based ADCs is presented. Implemented in 90nm CMOS process, on-chip…”
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A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement by Chao-Chang Chiu, Po-Hsien Huang, Lin, Moris, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee

“…Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The…”
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A 100-fps fluorescence lifetime imager in standard 0.13-µm CMOS by Field, Ryan M., Shepard, K. L.

“…A wide-field fluorescence lifetime imager capable of up to 100 frames per second (fps) is presented. The imager consists of a 64-by-64 array of low-noise…”
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A 22nm 2.5MB slice on-die L3 cache for the next generation Xeon® Processor by Wei Chen, Szu-Liang Chen, Siufu Chiu, Ganesan, Raghuraman, Lukka, Venkata, Mar, Wei Wing, Rusu, Stefan

“…The 20-way set associative 2.5MB slice ported L3 cache for the multi-core Xeon ® Processor uses 0.108 um 2 cell in a 22nm tri-gate technology with 2.7TB…”
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A 20nm 0.6V 2.1µW/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme by Fujiwara, H., Yabuuchi, M., Morimoto, M., Tanaka, K., Tanaka, M., Maeda, N., Tsukamoto, Y., Nii, K.

“…For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical…”
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Application of low-noise TIA ICs for novel sensing of MOSFET noise up to the GHz region by Ohmori, Kenji, Hasunuma, Ryu, Yamamoto, Satoshi, Tamura, Yoshinori, Hao Jiang, Ishihara, Noboru, Masu, Kazuya, Yamada, Keisaku

“…We have realized the characterization of MOSFET noise up to 3 GHz by locating a low-noise (LN) transimpedance amplifier (TIA) close to the devices to be tested…”
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A 4-element 60-GHz CMOS phased-array receiver with transformer-based hybrid-mode mixing and closed-loop beam-forming calibration by Liang Wu, Hiu Fai Leung, Li, Alvin, Zhiliang Hong, Yajie Qin, Luong, Howard C.

“…A 4-element 60-GHz phased-array receiver employs transformer-based hybrid-mode mixing featuring high linearity and high gain. Closed-loop beam-forming…”
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A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB by Brain, R., Baran, A., Bisnik, N., Chen, H.-P, Choi, S.-J, Chugh, A., Fradkin, M., Glassman, T., Hamzaoglu, F., Hoggan, E., Jahan, R., Jamil, M., Jan, C.-H, Jopling, J., Kan, H., Kasim, R., Kirby, S., Lahiri, S., Lee, B.-C, Lenski, D., Limb, J., Lindert, N., Musorrafiti, M., Neulinger, J., Rockford, L., Park, J., Singh, K., Staus, C., Steigerwald, J., Turkot, B., Vandervoorn, P., Venkatesan, R., Wu, S., Yeh, J.-Y, Wang, Y., Zhang, Z., Zhang, K.

“…A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and…”
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A 10V fully-integrated bidirectional SC ladder converter in 0.13µm CMOS using nested-bootstrapped switch cells by Dougherty, Christopher M., Lin Xue, Pulskamp, Jeffrey, Bedair, Sarah, Polcawich, Ronald, Morgan, Brian, Bashirullah, Rizwan

“…This paper presents a fully-integrated bidirectional SC ladder converter in 0.13μm 1.2V/3.3V triple-well CMOS with peak output voltage of ~10V. The converter…”
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A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC by Nandwana, Romesh Kumar, Saxena, Saurabh, Elshazly, Amr, Mayaram, Kartikeya, Hanumolu, Pavan Kumar

“…A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process,…”
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A ripple voltage sensing MPPT circuit for ultra-low power microsystems by Inhee Lee, Suyoung Bang, Dongmin Yoon, Myungjoon Choi, Seokhyeon Jeong, Sylvester, Dennis, Blaauw, David

“…We propose a maximum power point tracking (MPPT) circuit for micro-scale sensor systems that measures ripple voltages in a switched capacitor energy harvester…”
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A −90dBm sensitivity wireless transceiver using VCO-PA-LNA-switch-modulator co-design for low power insect-based wireless sensor networks by Sayilir, Serkan, Loke, Wing-Fai, Jangjoon Lee, Epstein, Benjamin, Rhodes, David L., Byunghoo Jung

“…This paper presents a wireless transceiver for WSNs using insects. It employs current reuse, switch-less switching, and fast PLL on/off switching techniques to…”
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