Search Results - "2011 International Electron Devices Meeting"

Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation by Khan, A. I., Yeung, C. W., Chenming Hu, Salahuddin, S.

“…A design methodology of ferroelectric (FE) negative capacitance FETs (NCFETs) based on the concept of capacitance matching is presented. A new mode of NCFET…”
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Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction by Suri, M., Bichler, O., Querlioz, D., Cueto, O., Perniola, L., Sousa, V., Vuillaume, D., Gamrat, C., DeSalvo, B.

“…We demonstrate a unique energy efficient methodology to use Phase Change Memory (PCM) as synapse in ultra-dense large scale neuromorphic systems. PCM devices…”
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Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors by Boscke, T. S., Muller, J., Brauhaus, D., Schroder, U., Bottger, U.

“…We report the discovery of ferroelectricity in crystalline hafnium silicon oxide. If HfO 2 based thin films, at a composition where the tetragonal phase is not…”
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Statistical variability and reliability in nanoscale FinFETs by Xingsheng Wang, Brown, A. R., Binjie Cheng, Asenov, A.

“…A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of…”
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High performance SiC trench devices with ultra-low ron by Nakamura, T., Nakano, Y., Aketa, M., Nakamura, R., Mitani, S., Sakairi, H., Yokotsuji, Y.

“…We have developed SiC trench structure Schottky diodes and SiC double-trench MOSFETs. We succeeded in improving device performance by the reduction of the…”
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On the stochastic nature of resistive switching in metal oxide RRAM: Physical modeling, monte carlo simulation, and experimental characterization by Shimeng Yu, Ximeng Guan, Wong, H.-S Philip

“…The origin of switching parameter variations in metal oxide resistive switching random access memory (RRAM) is studied. The stochastic formation/rupture of the…”
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Analytic modeling of the bias temperature instability using capture/emission time maps by Grasser, T., Wagner, P., Reisinger, H., Aichinger, T., Pobegen, G., Nelhiebel, M., Kaczer, B.

“…Despite a number of recent advances made in the understanding of the bias temperature instability (BTI), there is still no simple model available which can…”
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1-nm-thick EOT high mobility Ge n- and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation by Rui Zhang, Taoka, N., Po-Chin Huang, Takenaka, M., Takagi, S.

“…An ultrathin EOT Al 2 O 3 /GeO x /Ge gate stack with a superior GeO x /Ge MOS interface has been fabricated with a plasma post oxidation method. The properties…”
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The evolution of scaling from the homogeneous era to the heterogeneous era by Bohr, M.

“…Traditional MOSFET scaling served our industry well for more than three decades by providing continuous improvements in transistor performance, power and cost…”
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Physical mechanisms of endurance degradation in TMO-RRAM by Chen, B., Lu, Y., Gao, B., Fu, Y. H., Zhang, F. F., Huang, P., Chen, Y. S., Liu, L. F., Liu, X. Y., Kang, J. F., Wang, Y. Y., Fang, Z., Yu, H. Y., Li, X., Wang, X. P., Singh, N., Lo, G. Q., Kwong, D. L.

“…We report, for the first time, three types of endurance failure behaviors in TMO based RRAM. New physical mechanisms are proposed to clarify the physical…”
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One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications by Jiun-Jia Huang, Yi-Ming Tseng, Wun-Cheng Luo, Chung-Wei Hsu, Tuo-Hung Hou

“…Lack of a suitable selection device to suppress sneak current has impeded the development of 4F 2 crossbar memory array utilizing stable and scalable bipolar…”
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Realization of vertical resistive memory (VRRAM) using cost effective 3D process by Baek, I. G., Park, C. J., Ju, H., Seong, D. J., Ahn, H. S., Kim, J. H., Yang, M. K., Song, S. H., Kim, E. M., Park, S. O., Park, C. H., Song, C. W., Jeong, G. T., Choi, S., Kang, H. K., Chung, C.

“…Vertical ReRAM (VRRAM) has been realized with modification of Vertical NAND (VNAND) process and architecture as a cost-effective and extensible technology for…”
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Experimental and theoretical study of electrode effects in HfO2 based RRAM by Cagli, C., Buckley, J., Jousseaume, V., Cabout, T., Salaun, A., Grampeix, H., Nodin, J. F., Feldis, H., Persico, A., Cluzel, J., Lorenzi, P., Massari, L., Rao, R., Irrera, F., Aussenac, F., Carabasse, C., Coue, M., Calka, P., Martinez, E., Perniola, L., Blaise, P., Fang, Z., Yu, Y. H., Ghibaudo, G., Deleruyelle, D., Bocquet, M., Muller, C., Padovani, A., Pirrotta, O., Vandelli, L., Larcher, L., Reimbold, G., de Salvo, B.

“…In this work, the impact of Ti electrodes on the electrical behaviour of HfO 2 -based RRAM devices is conclusively clarified. To this aim, devices with Pt, TiN…”
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Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation by Radosavljevic, M., Dewey, G., Basu, D., Boardman, J., Chu-Kung, B., Fastenau, J. M., Kabehie, S., Kavalieros, J., Le, V., Liu, W. K., Lubyshev, D., Metz, M., Millard, K., Mukherjee, N., Pan, L., Pillarisetty, R., Rachmady, W., Shah, U., Then, H. W., Chau, R.

“…In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled…”
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Advances, challenges and opportunities in 3D CMOS sequential integration by Batude, P., Vinet, M., Previtali, B., Tabone, C., Xu, C., Mazurier, J., Weber, O., Andrieu, F., Tosti, L., Brevard, L., Sklenard, B., Coudrain, P., Bobba, S., Ben Jamaa, H., Gaillardon, P., Pouydebasque, A., Thomas, O., Le Royer, C., Hartmann, J., Sanchez, L., Baud, L., Carron, V., Clavelier, L., De Micheli, G., Deleonibus, S., Faynot, O., Poiroux, T.

“…3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges…”
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GeSn technology: Extending the Ge electronics roadmap by Gupta, S., Chen, R., Magyari-Kope, B., Hai Lin, Bin Yang, Nainani, A., Nishi, Y., Harris, J. S., Saraswat, K. C.

“…First principles study showed indicated band gap of Ge can be tuned by alloying with Sn and metastable GeSn alloys can be synthesized at or above room…”
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3D copper TSV integration, testing and reliability by Farooq, M. G., Graves-Abe, T. L., Landers, W. F., Kothandaraman, C., Himmel, B. A., Andry, P. S., Tsang, C. K., Sprogis, E., Volant, R. P., Petrarca, K. S., Winstel, K. R., Safran, J. M., Sullivan, T. D., Chen, F., Shapiro, M. J., Hannon, R., Liptak, R., Berger, D., Iyer, S. S.

“…Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no…”
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PRAM cell technology and characterization in 20nm node size by Kang, M. J., Park, T. J., Kwon, Y. W., Ahn, D. H., Kang, Y. S., Jeong, H., Ahn, S. J., Song, Y. J., Kim, B. C., Nam, S. W., Kang, H. K., Jeong, G. T., Chung, C. H.

“…We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required…”
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Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic applications by Mohata, D. K., Bijesh, R., Mujumdar, S., Eaton, C., Engel-Herbert, R., Mayer, T., Narayanan, V., Fastenau, J. M., Loubychev, D., Liu, A. K., Datta, S.

“…Type II arsenide/antimonide compound semiconductor with highly staggered GaAs 0.35 Sb 0.65 /In 0.7 Ga 0.3 As hetero-junction is used to demonstrate hetero…”
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Deeply-scaled self-aligned-gate GaN DH-HEMTs with ultrahigh cutoff frequency by Shinohara, K., Regan, D., Corrion, A., Brown, D., Burnham, S., Willadsen, P. J., Alvarado-Rodriguez, I., Cunningham, M., Butler, C., Schmitz, A., Kim, S., Holden, B., Chang, D., Lee, V., Ohoka, A., Asbeck, P. M., Micovic, M.

“…We report record DC and RF performance in deeply-scaled self-aligned gate (SAG) GaN-HEMTs operating in both depletion-mode (D-mode) and enhancement-mode…”
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