Search Results - "2011 IEEE Hot Chips 23 Symposium (HCS)"

Refine Results
  1. 1
    Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge

    Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge by Rotem, Efi, Naveh, Alon, Rajwan, Doron, Ananthakrishnan, Avinash, Weissmann, Eli

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design and architectures, processing…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  2. 2
    Bandwidth engine® serial memory chip breaks 2 billion accesses/sec

    Bandwidth engine® serial memory chip breaks 2 billion accesses/sec by Miller, Michael J.

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…Presents a collection of slides covering the following topics: network memory access; bandwidth engine design; memory interface; and multicore process…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  3. 3
    2nd Generation Intel® Core Processor Family: Intel® Core i7, i5 and i3

    2nd Generation Intel® Core Processor Family: Intel® Core i7, i5 and i3 by Lempel, Oded

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on Intel's i7, i5, and i3 family of core processor products. Some of…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  4. 4
    Poulson: An 8 core 32 nm next generation Intel® Itanium® processor

    Poulson: An 8 core 32 nm next generation Intel® Itanium® processor by Undy, Steve

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…Presents a collection of slides covering the following topics: 8-socket topology; Poulson core; Itanium; instruction level parallelism; memory parallelism;…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  5. 5
    The Intel® Quick Sync Video technology in the 2nd-generation Intel Core processor family

    The Intel® Quick Sync Video technology in the 2nd-generation Intel Core processor family by Hong Jiang

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  6. 6
    Hybrid memory cube (HMC)

    Hybrid memory cube (HMC) by Pawlowski, J. Thomas

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, system architectures;…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  7. 7
    TILE-Gx100 ManyCore processor: Acceleration interfaces and architecture

    TILE-Gx100 ManyCore processor: Acceleration interfaces and architecture by Ramey, Carl

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  8. 8
    Xilinx Zynq-7000 EPP: An extensible processing platform family

    Xilinx Zynq-7000 EPP: An extensible processing platform family by Rajagopalan, Vidya, Boppana, Vamsi, Dutta, Sandeep, Taylor, Brad, Wittig, Ralph

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  9. 9
    SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips

    SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips by Dhodapkar, Ashutosh, Lauterbach, Gary, Lie, Sean, Mallick, Dhiraj, Bauman, Jim, Kanthadai, Sundar, Kuzuhara, Toru, Shen, Gene, Min Xu, Zhang, Chris

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  10. 10
    1TOPS/W software programmable media processor

    1TOPS/W software programmable media processor by Moloney, David

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  11. 11
    Electrons, photons, phonons, wave, bits, and industrial design: Microsoft kinect sensor: Hot chips 23

    Electrons, photons, phonons, wave, bits, and industrial design: Microsoft kinect sensor: Hot chips 23 by Yee, Dawson, McEldowney, Scott

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…Presents a collection of slides covering the following topics: Microsoft Kinect sensor design considerations, product requirements, and design tactics; and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  12. 12
    Practical power gating and dynamic voltage/frequency scaling

    Practical power gating and dynamic voltage/frequency scaling by Kosonocky, Stephen

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on practical power gating and dynamic voltage and frequency scaling…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  13. 13
    The Cavium 32 Core OCTEON II 68xx

    The Cavium 32 Core OCTEON II 68xx by Kessler, R. E.

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…Presents a collection of slides covering the following topics: Cavium 32 core OCTEON II 68xx; power scalability; cache coherence; interconnect bandwidth;…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  14. 14
    The Blue Gene/Q Compute chip

    The Blue Gene/Q Compute chip by Haring, Ruud

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  15. 15
    VENICE: A compact vector processor for FPGA applications

    VENICE: A compact vector processor for FPGA applications by Severance, Aaron, Lemieux, Guy

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on VENICE (Vector Extensions to NIOS Implemented Compactly and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  16. 16
    Intel's digital random number generator (DRNG)

    Intel's digital random number generator (DRNG) by Cox, George, Dike, Charles, Johnston, D. J.

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  17. 17
    High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer"

    High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer" by White, Sean

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  18. 18
    The utility of fast active messages on many-core chips: Efficient supercomputing project

    The utility of fast active messages on many-core chips: Efficient supercomputing project by Harting, R. Curtis, Parikh, Vishal, Dally, William J.

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…This article consists of a collection of slides from the author's conference presentation on the deployment of many core chips for supercomputing applications…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  19. 19
    One billion packet per second frame processing pipeline

    One billion packet per second frame processing pipeline by Davies, Mike

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…Presents a collection of slides covering the following topics: frame processing pipeline; system design; processing capability; Fulcrum Ethernet switch chip…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  20. 20
    ARM processor evolution: Bringing high performance to mobile devices

    ARM processor evolution: Bringing high performance to mobile devices by Segars, Simon

    Published in 2011 IEEE Hot Chips 23 Symposium (HCS) (01-08-2011)
    “…Presents a collection of slides covering the following topics: mobile computing; ubiquitous computing; silicon scaling; system-on-chip; and multicore CPU…”
    Get full text
    Conference Proceeding
    Save to List
    Saved in:

Search Tools: