Search Results - "2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)"

Reduction of lead free solder aging effects using doped SAC alloys by Zijie Cai, Yifei Zhang, Suhling, Jeffrey C, Lall, Pradeep, Johnson, R Wayne, Bozack, Michael J

“…The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to…”
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Thermal stress induced delamination of through silicon vias in 3-D interconnects by Lu, Kuan H, Suk-Kyu Ryu, Qiu Zhao, Xuefeng Zhang, Im, Jay, Rui Huang, Ho, Paul S

“…In this paper we investigated the interfacial delamination of through silicon via (TSV) structures under thermal cycling or processing. First finite element…”
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3-D Thin film interposer based on TGV (Through Glass Vias): An alternative to Si-interposer by Töpper, Michael, Ndip, Ivan, Erxleben, Robert, Brusberg, Lars, Nissen, Nils, Schröder, Henning, Yamamoto, Hidefumi, Todt, Guido, Reichl, Herbert

“…Interposers for SiP will become more and more important for advanced electronic systems. But through substrate vias are essential for the 3-D integration…”
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TSV manufacturing yield and hidden costs for 3D IC integration by Lau, John H

“…3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general, the TSV (through-silicon-via)…”
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Through-package-via formation and metallization of glass interposers by Sukumaran, Vijay, Qiao Chen, Fuhan Liu, Kumbhat, Nitesh, Bandyopadhyay, Tapobrata, Chan, Hunter, Sunghwan Min, Nopper, Christian, Sundaram, Venky, Tummala, Rao

“…Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus…”
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Cu/Sn microbumps interconnect for 3D TSV chip stacking by Agarwal, Rahul, Wenqi Zhang, Limaye, Paresh, Labie, Riet, Dimcic, Biljana, Phommahaxay, Alain, Soussan, Philippe

“…The electronics industry is increasingly looking to 3D integration in order to address the ever continuing product needs of miniaturization and performance…”
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A comparison of thin film polymers for Wafer Level Packaging by Töpper, Michael, Fischer, Thorsten, Baumgartner, Tobias, Reichl, Herbert

“…Polymers are a key building block for all WLP and related technologies like IPD (integrated passives devices) and 3D-SiP (system in Package). A couple of…”
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IMC bonding for 3D interconnection by Sakuma, K, Sueoka, K, Kohara, S, Matsumoto, K, Noma, H, Aoki, T, Oyama, Y, Nishiwaki, H, Andry, P S, Tsang, C K, Knickerbocker, J U, Orii, Y

“…We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike…”
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Prognostics using Kalman-Filter models and metrics for risk assessment in BGAs under shock and vibration loads by Lall, Pradeep, Lowe, Ryan, Goebel, Kai

“…Structural damage to BGA interconnects incurred during vibration testing has been monitored in the pre-failure space using resistance spectroscopy based state…”
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Terabit/s-class 24-channel bidirectional optical transceiver module based on TSV Si carrier for board-level interconnects by Doany, Fuad E, Lee, Benjamin G, Schow, Clint L, Tsang, Cornelia K, Baks, Christian, Kwark, Young, John, Richard, Knickerbocker, John U, Kash, Jeffrey A

“…We report here on the design, fabrication and characterization of highly-integrated 3-D Optochips consisting of a Si carrier platform with 4 flip-chip attached…”
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Assembly and reliability characterization of 3D chip stacking with 30μm pitch lead-free solder micro bump interconnection by Chau-Jie Zhan, Chun-Chih Chuang, Jing-Ye Juang, Su-Tsai Lu, Tao-Chih Chang

“…Recently, the three-dimensional chip stacking technology with fine pitch and high input/output interconnects has emerged due to the requirements of…”
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Fine pitch chip interconnection technology for 3D integration by Jihwan Hwang, Jongyeon Kim, Woonseong Kwon, Unbyoung Kang, Taeje Cho, Sayoon Kang

“…3D-IC packaging using through silicon via technology has been extensively developed to meet small form factor and low power consumption for next generation…”
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Studies on electrical performance and thermal stress of a silicon interposer with TSVs by Sunohara, Masahiro, Sakaguchi, Hideaki, Takano, Akihito, Arai, Rie, Murayama, Kei, Higashi, Mitsutoshi

“…The silicon interposer had been desired to have high Input/Output (I/O) counts and fine wirings such as the global wiring of devices. High integration of…”
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Challenges of Cu wire bonding on low-k/Cu wafers with BOA structures by Chu-Chung Lee, Higgins, Leo M

“…This study describes the development of a Cu wire bond assembly solution for ICs using low dielectric constant (low K) dielectrics and Cu interconnect, with…”
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Full characterization of Cu/Cu direct bonding for 3D integration by Taibi, Rachid, Di Cioccio, Léa, Chappaz, Cedrick, Chapelon, Laurent-Luc, Gueguen, Pierric, Dechamp, Jérome, Fortunier, Roland, Clavelier, Laurent

“…This paper presents the latest results on electrical characterization of wafer to wafer structures made by direct copper bonding. The bonding was achieved at…”
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Slow wave and dielectric quasi-TEM modes of Metal-Insulator-Semiconductor (MIS) structure Through Silicon Via (TSV) in signal propagation and power delivery in 3D chip package by Jun So Pak, Jonghyun Cho, Joohee Kim, Junho Lee, Hyungdong Lee, Kunwoo Park, Joungho Kim

“…The effects of slow wave and dielectric quasi-TEM modes due to MIS (Metal-Insulator-Semiconductor) structure TSV (Through-Silicon-Via) are analyzed by using…”
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Effects of fine size lead-free solder ball on the interfacial reactions and joint reliability by Yong-Sung Park, Yong-Min Kwon, Jeong-Tak Moon, Young-Woo Lee, Jae-Hong Lee, Kyung-Wook Paik

“…As the trend of smaller mobile electronic products, smaller solder balls are needed for electronic packages such as chip scale package (CSP). The purpose of…”
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CMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration by Bing Dang, Andry, Paul, Tsang, Cornelia, Maria, Joana, Polastre, Robert, Trzcinski, Robert, Prabhakar, Aparna, Knickerbocker, John

“…This paper reports a thin wafer handling technology that is compatible to CMOS processing conditions to enable 3D integration and assembly with high throughput…”
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Low temperature PECVD of dielectric films for TSV applications by Archard, D, Giles, K, Price, A, Burgess, S, Buchanan, K

“…The effects of a novel, low-temperature (<; 200 °C) PECVD TEOS SiO process on via step coverage and blanket film electrical performance are investigated and…”
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Flip-chip integrated silicon photonic bridge chips for sub-picojoule per bit optical links by Thacker, Hiren D, Ying Luo, Jing Shi, Shubin, Ivan, Lexau, Jon, Xuezhe Zheng, Guoliang Li, Jin Yao, Costa, Joannes, Pinguet, Thierry, Mekis, Attila, Po Dong, Shirong Liao, Dazeng Feng, Asghari, Mehdi, Ron Ho, Raj, Kannan, Mitchell, James G, Krishnamoorthy, Ashok V, Cunningham, John E

“…Silicon photonics holds tremendous promise as an energy and bandwidth efficient interconnect technology for chip-to-chip and within-chip communications in…”
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