Search Results - "2009 IEEE Asian Solid-State Circuits Conference"

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  1. 1

    A low-offset latched comparator using zero-static power dynamic offset cancellation technique by Miyahara, M., Matsuzawa, A.

    “…A low-offset latched comparator using new dynamic offset cancellation technique is proposed. The new technique achieves low offset voltage without…”
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    Conference Proceeding
  2. 2

    A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications by Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, Nai-Kuan Chou, Chorng-Kuang Wang

    “…This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. Splitting comparator and…”
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    Conference Proceeding
  3. 3

    An accurate current reference using temperature and process compensation current mirror by Byung-Do Yang, Young-Kyu Shin, Jee-Sue Lee, Yong-Kyu Lee, Keun-Chul Ryu

    “…In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent…”
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    Conference Proceeding
  4. 4

    Weak inversion for ultra low-power and very low-voltage circuits by Vittoz, E.A.

    “…This paper discusses techniques, limitations and possible future developments of circuits based on transistors operated in the weak inversion (w.i.) mode, also…”
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    Conference Proceeding
  5. 5

    Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating by Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M., Kondo, M.

    “…Geyser-1, a prototype MIPS R3000 CPU with fine grain runtime PG for major computational components in the execution stage is available. Function units such as…”
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  6. 6

    A real-time ECG QRS detection ASIC based on wavelet multiscale analysis by Phyu, Myint Wai, Zheng, Yuanjin, Zhao, Bin, Xin, Liu, Wang, Yi Sheng

    “…This paper presents for the first time Electrocardiograph (ECG) QRS detection algorithm implemented in Application Specific Integrated Circuit (ASIC). The…”
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    Conference Proceeding
  7. 7

    A low power 60GHz OOK transceiver system in 90nm CMOS with innovative on-chip AMC antenna by Lin, Fujiang, Brinkhoff, James, Kang, Kai, Pham, Duy Dong, Yuan, Xiaojun

    “…Building on an efficient active and passive device modeling strategy, a 60 GHz OOK transceiver system including on-chip antenna in 90 nm CMOS is designed. The…”
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    Conference Proceeding
  8. 8

    A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS by Yanfei Chen, Tsukamoto, S., Kuroda, T.

    “…A 9 b 100 MS/s successive approximation register (SAR) ADC has been implemented in 65 nm CMOS, with an active area of 0.012 mm 2 . A tri-level based charge…”
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    Conference Proceeding
  9. 9

    A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier by Sinangil, M.E., Verma, N., Chandrakasan, A.P.

    “…8 T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This…”
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    Conference Proceeding
  10. 10

    A 6bit, 7mW, 250fJ, 700MS/s subranging ADC by Asada, Y., Yoshihara, K., Urano, T., Miyahara, M., Matsuzawa, A.

    “…A 6 bit, 7 mW, 700 MS/s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging…”
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    Conference Proceeding
  11. 11

    On-die parameter extraction from path-delay measurements by Takahashi, T., Uezono, T., Shintani, M., Masu, K., Sato, T.

    “…Device-parameter estimation through path-delay measurement, which facilitates fast on-die performance prediction and diagnosis, is proposed. With the proposed…”
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    Conference Proceeding
  12. 12

    A 45nm 8-core enterprise Xeon® processor by Rusu, S., Tam, S., Muljono, H., Ayers, D., Chang, J., Varada, R., Ratta, M., Vora, S.

    “…A 2.3 B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24 MB shared L3 cache was implemented in a 45 nm 9-metal process. Multiple clock and…”
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    Conference Proceeding
  13. 13

    A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance by Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin, Soon-Jyh Chang

    “…This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-¿m…”
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    Conference Proceeding
  14. 14

    A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity by Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Tsung-Hsin Yu, Jinn-Yeh Chien, Chen, W.D., Chi-Chang Lu, Wei-Chih Chen, Fu, J., Yang, S.J., Chien-Hung Chen, Kuo-Liang Deng, Wen, C.H., Wang, L.Y.

    “…A PCI Express 2.0/1.0 compatible SERDES system had been fabricated in TSMC 40 nm CMOS technology. With the implementation of one lane transceiver, PLL, and…”
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    Conference Proceeding
  15. 15

    A 130-μW, 64-channel spike-sorting DSP chip by Karkare, V., Gibson, S., Markovic, D.

    “…Spike sorting is an important processing step in various neuroscientific and clinical studies. An on-chip spike-sorting DSP must provide data-rate reduction…”
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    Conference Proceeding
  16. 16

    A 3mW 12b 10MS/s sub-range SAR ADC by Hung-Wei Chen, Yu-Hsun Liu, Yu-Hsiang Lin, Hsin-Shu Chen

    “…This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping…”
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    Conference Proceeding
  17. 17

    A 0.9-3.0 GHz fully integrated tunable CMOS power amplifier for multi-band transmitters by Imanishi, D., Okada, K., Matsuzawa, A.

    “…A tunable power amplifier (PA) from 0.9 GHz to 3.0 GHz is presented. This paper proposes an output impedance tuning method by using resistive feedback and a…”
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    Conference Proceeding
  18. 18

    Inductorless 1-10.5 GHz wideband LNA for multistandard applications by Hampel, S.K., Schmitz, O., Tiebout, M., Rolfes, I.

    “…This article presents the design of a fully integrated inductorless LNA for wireless applications including WLAN, Bluetooth and UWB. The circuit was fabricated…”
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    Conference Proceeding
  19. 19

    An extended XY coil for noise reduction in inductive-coupling link by Saito, M., Kasuga, K., Takeya, T., Miura, N., Kuroda, T.

    “…Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip interconnections. An XY-coil layout style allows logic…”
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    Conference Proceeding
  20. 20

    A CBSC second-order sigma-delta modulator in 3μm LTPS-TFT technology by Wei-Ming Lin, Chan-Fei Lin, Shen-Iuan Liu

    “…A second-order sigma-delta modulator has been implemented in 3 μm low-temperature poly-silicon thin-film transistor (LTPS-TFT) technology. Since the LTPS-TFT…”
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