Search Results - "2008 IEEE International Test Conference"

Testing Techniques for Hardware Security by Majzoobi, M., Koushanfar, F., Potkonjak, M.

“…System security has emerged as a premier design requirement. While there has been an enormous body of impressive work on testing integrated circuits (ICs)…”
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Optimized Circuit Failure Prediction for Aging: Practicality and Promise by Agarwal, M., Balakrishnan, V., Bhuyan, A., Kyunglok Kim, Paul, B.C., Wenping Wang, Bo Yang, Yu Cao, Mitra, S.

“…Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This…”
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Frequency and Power Correlation between At-Speed Scan and Functional Tests by Sde-Paz, S., Salomon, E.

“…At-speed scan is a key technique in modern IC testing. One of its drawbacks, with respect to functional tests, is its excessive power consumption leading to…”
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Low Power Scan Shift and Capture in the EDT Environment by Czysz, D., Kassab, M., Lin, X., Mrugalski, G., Rajski, J., Tyszer, J.

“…This paper presents a new and comprehensive power-aware test scheme compatible with a test compression environment. The key contribution of the paper is a…”
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Launch-on-Shift-Capture Transition Tests by Park, I., McCluskey, E.J.

“…The two most popular transition tests are launch-on-shift (LOS) test and launch-on-capture (LOC) test. The LOS and LOC tests differ in their launch mechanisms,…”
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VAST: Virtualization-Assisted Concurrent Autonomous Self-Test by Inoue, H., Yanjing Li, Mitra, S.

“…Virtualization-assisted concurrent, autonomous self-test, or VAST, enables a multi-/many-core system to test itself, concurrently during normal operation,…”
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A Study of Outlier Analysis Techniques for Delay Testing by Wu, S.H., Drmanac, D., Wang, L.-C.

“…This work provides a survey study of several outlier analysis techniques and compares their effectiveness in the context of delay testing. Three different…”
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Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing by Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Miyase, K.

“…Yield loss caused by excessive power supply noise has become a serious problem in at-speed scan testing. Although X-filling techniques are available to reduce…”
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Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects by Yilmaz, M., Chakrabarty, K., Tehranipoor, M.

“…Timing-related failures in high-performance integrated circuits are being increasingly dominated by small-delay defects (SDDs). Such delay faults are caused by…”
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Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs by Ho Fai Ko, Kinsman, A.B., Nicolici, N.

“…Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-time observability of the circuit's internal nodes. In this…”
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RTL Error Diagnosis Using a Word-Level SAT-Solver by Mirzaeian, S., Feijun Zheng, Cheng, K.-T.T.

“…We propose a novel methodology for design error diagnosis in the HDL description using a word-level solver. In this approach, the patterns that result in…”
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Peak Power Reduction Through Dynamic Partitioning of Scan Chains by Almukhaizim, S., Sinanoglu, O.

“…Serial shift operations in scan-based testing impose elevated levels of power dissipation, endangering the reliability of the chip being tested. Scan chain…”
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A Cost Analysis Framework for Multi-core Systems with Spares by Shamshiri, S., Lisherness, P., Sung-Jui Pan, Kwang-Ting Cheng

“…It becomes increasingly difficult to achieve a high manufacturing yield for multi-core chips due to larger chip sizes, higher device densities, and greater…”
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A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems by Shazli, S.Z., Abdul-Aziz, M., Tahoori, M.B., Kaeli, D.R.

“…Soft errors due to alpha and cosmic particles are a growing reliability threat to information systems. In this work, a methodology is developed to analyze the…”
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Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data by Sharma, M., Benware, B., Lei Ling, Abercrombie, D., Lee, L., Keim, M., Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Lin, R., Man, A.

“…Yield enhancements in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. In…”
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An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis by Xiaochun Yu, Blanton, R.D.

“…A multiple defect diagnosis methodology consisting of a defect site identification and elimination method, a path-based defect site elimination method, and a…”
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Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks by Nadeau-Dostie, B., Takeshita, K., Cote, J.-F.

“…The BurstModetrade test clocking methodology, first presented in, is improved to handle circuits with synchronous clocks of different frequencies. An on-chip…”
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Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality by Eichenberger, S., Geuzebroek, J., Hora, C., Kruseman, B., Majhi, A.

“…With test quality being an imperative, this paper presents a methodology on how to apply volume scan diagnosis - known from the field of yield learning - to…”
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On-chip Programmable Capture for Accurate Path Delay Test and Characterization by Tayade, R., Abraham, J.A.

“…The increasing gap between modern chip frequencies and test clock frequencies provided by external test equipment, makes at-speed delay testing a challenge. We…”
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Using Implications for Online Error Detection by Nepal, K., Alves, N., Dworak, J., Bahar, R.I.

“…In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We…”
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