Search Results - "2008 14th IEEE International On-Line Testing Symposium"

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation by Shafik, R.A., Rosinger, P., Al-Hashimi, B.M.

“…In this paper, we propose a new SystemC-based fault injection technique that has improved fault representation in visible and on-the-fly data and signal…”
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Physical Demonstration of Polymorphic Self-Checking Circuits by Ruzicka, R., Sekanina, L., Prokop, R.

“…Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure…”
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Reliability in Application Specific Mesh-Based NoC Architectures by Refan, F., Alemzadeh, H., Safari, S., Prinetto, P., Navabi, Z.

“…Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield…”
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New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability by Richter, M., Oberlaender, K., Goessel, M.

“…This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are…”
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Special Session 4: Reliability and Circuit Simulation by Aitken, Rob

“…The document was not made available for publication as part of the conference proceedings…”
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Special Session 3 - Panel: SER in Automotive: what is the impact of the AEC Q100-G spec? by Heijmen, Tino

“…Summary form only given, as follows. A record of the panel discussion was not made available for publication as part of the conference proceedings. In May 2007…”
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Soft Error Protection Techniques by Mitra, Subhasish

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Soft Error Rates of Hardened Sequentials utilizing Local Redundancy by Seifert, N.

“…Process scaling is well know to increase overall chip-level soft error rates (SER) if no additional mitigation techniques are applied [Seifert04]. The purpose…”
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Modeling and Simulation of Circuit Aging in Scaled CMOS Design by Yu Kao

“…The document was not made available for publication as part of the conference proceedings…”
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Special Session 1: Radiation Hardening Techniques by Seifert, Norbert

“…Summary form only given, as follows. While the industry does not agree on the details of soft error rate per device trends, an increase of chip-level upset…”
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Totally Fault Tolerant RNS Based FIR Filters by Pontarelli, S., Cardarilli, G.C., Re, M., Salsano, A.

“…In this paper, the design of a finite impulse response (FIR) filter with fault tolerant capabilities based on the residue number system is analyzed…”
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A New Approach for Transient Fault Injection Using Symbolic Simulation by Darbari, A., Al Hashimi, B., Harrod, P., Bradley, D.

“…One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of…”
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Soft-Error Vulnerability of Sub-100-nm Flip-Flops by Heijmen, T.

“…The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error…”
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A Built-In Self-Test Scheme for Soft Error Rate Characterization by Sanyal, A., Alam, S.M., Kundu, S.

“…Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse…”
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A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs by Perez, W.J., Velasco, J., Ravotto, D., Sanchez, E., Reorda, M.S.

“…Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while…”
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On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs by Battezzati, N., Gerardin, S., Manuzzato, A., Paccagnella, A., Rezgui, S., Sterpone, L., Violante, M.

“…Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non…”
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Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips by Zajac, P., Collet, J.H., Napieralski, A.

“…The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To…”
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On-Line Failure Detection and Confinement in Caches by Abella, J., Chaparro, P., Vera, X., Carretero, J., Gonzalez, A.

“…Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects…”
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Message from General Chair(s)

“…Presents the introductory welcome message from the conference proceedings…”
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Test Technology Educational Program (TTEP) 2008 Full-Day Tutorial

“…Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for…”
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