Search Results - "2007 International Symposium on Integrated Circuits"

Novel 10-T full adders realized by GDI structure by Po-Ming Lee, Chia-Hao Hsu, Yun-Hsiun Hung

“…A full adder is one of the most commonly used digit circuit components, many improvements have been made to refine the architecture of a full adder. In this…”
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Design of a High Performance Charge Pump Circuit for Low Voltage Phase-locked Loops by Yuan Sun, Liter Siek, Pengyu Song

“…In this paper, the design of a 1.2 V charge pump circuit suitable for PLL-based frequency synthesizer with low spurious tone requirement is presented. The…”
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Interfacing Cores and Routers in Network-on-Chip Using GALS by Kundu, S., Chattopadhyay, S.

“…Network-on-Chip (NoC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is…”
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C-less and R-less Low-Frequency ASK Demodulator for Wireless Implantable Devices by Tzung-Je Lee, Ching-Li Lee, Yan-Jhih Ciou, Chi-Chun Huang, Chua-Chin Wang

“…A miniature ASK demodulator without any passive elements, i.e., R or C, for implantable devices is presented in the paper. The noise margin of the envelope…”
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A Fast Motion Estimation Algorithm for SAD Optimization in Sub-pixel by Dong-kyun Park, Hyo-moon Cho, Sang-bok Cho, Jong-hwa Lee

“…The motion estimation is the most important technique in the image compression of the video standards. In the case of next generation standards in the video…”
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Low phase noise and Fast locking PLL Frequency Synthesizer for a 915MHz ISM Band by Seung-Hoon Kim, Sang-bock Cho

“…In this paper, Low phase noise and Fast locking PLL Frequency Synthesizer in a 0.18-um CMOS process is presented. This thesis application is the 915MHz ISM…”
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Adiabatic Flip-Flops for Power-Down Applications by Dong Zhou, Jianping Hu, Ling Wang

“…This paper presents adiabatic flip-flops with data-retention function, which are realized with the CPAL (complementary pass-transistor adiabatic logic)…”
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Three Dimensional (3D) n-gate MOSFET by Theng, A.L., Goh, W.L., Chan, Y.T., Tee, K.M., Chan, L., Ng, C.M.

“…The concept of a three-dimensional (3D) n-gate MOSFET device SOI substrate has been proposed and developed in this work. This device consists of a rounded…”
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A Design of Analog Multiplier and Divider Using Current Controlled Current Differencing Buffered Amplifiers by Siripruchyanun, M.

“…A novel current-mode analog multiplier/divider, based on current controlled current differencing buffered amplifiers (CCCDBAs), is presented in this paper. The…”
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5 GHz 1.4 dB NF CMOS LNA integrated in 130 nm High Resistivity SOI technology by Gianesello, F., Gloria, D., Raynaud, C., Boret, S.

“…CMOS is today a good candidate for an optimum single chip implementation of both the analog and digital blocks in wireless mobile transceivers. Concerning…”
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A Low-Power Adiabatic Multiplier Based on Modified Booth Algorithm by Jianping Hu, Ling Wang, Tiefeng Xu

“…This paper presents an adiabatic array multiplier based on modified Booth algorithm. It is composed of Booth encoders, a multiplier array containing partial…”
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A Novel Static Dual Edge-Trigger Flip-flop for High-Frequency Low-Power Application by Goh Wang Ling, Yeo Kiat Seng, Zhang Wenle, Lim Hoe Gee

“…Abstract-In this paper, we propose a simple and novel Dual-edge-trigger flip-flop (DETFF). The design has a simple structure which consists of a XNOR pulse…”
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Analysis and Design of a High Efficiency Boost DC-DC Converter Based on Pulse-Frequency Modulation by Xin Liu, Shuxu Guo, Shuai Wang, Feng Xu, Guotong Du, Yuchun Chang

“…A high efficiency boost DC-DC converter controlled by current-limited and minimum off-time pulse-frequency modulation (PFM) mode is analyzed in this paper. The…”
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A Chopper Stabilized Pre-amplifier for Biomedical Signal Acquisition by Hanasusanto, G.A., Yuanjin Zheng

“…This paper presents a low-power and low-voltage pre-amplifier for biomedical signal acquisition application. The main blocks of the pre-amplifier consist of a…”
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Cost-Efficient Partially-Parallel Irregular LDPC Decoder with Message Passing Schedule by Xing Li, Abe, Y., Shimizu, K., Zhen Qiu, Ikenaga, T., Goto, S.

“…This paper proposes an improved message passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing…”
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A Low-Cost 256-Point FFT Processor for Portable Speech and Audio Applications by Chao Wang, Woon-Seng Gan, Ching Chuen Jong, Jianwen Luo

“…In this paper, a low-cost 256-point FFT processor design is presented for portable speech and audio applications. After an intensive review of existing FFT…”
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An Improved Universal CMOS Current-Mode Analog Function Synthesizer by Abuelma'atti, M.T., Al-Yahia, N.M.

“…A CMOS integratable current-mode analog function synthesizer circuit is presented. The proposed circuit is based on approximating the required function using…”
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Analysis and Design of RC Polyphase Network for Quadrature Signal Generation in the 2.45GHz ISM Band by Xie, J., Do, A., Yeo, K.S., Boon, C.C.

“…This paper presents a detailed analysis of the RC polyphase network. A new approach based on very basic principles is used to derive the transfer functions of…”
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High Speed Ultra Wide Band Comparator in Deep Sub-Micron CMOS by Mohan, A., Zayegh, A., Stojcevski, A., Veljanovski, R.

“…This paper presents the implementation of a high speed low power over sampled CMOS comparator for use in a reconfigurable flash analog to digital converter…”
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Evaluation of Traffic Pattern Effect on Power Consumption in Mesh and Torus Network-on-Chips by Koohi, S., Mirza-Aghatabar, M., Hessabi, S.

“…Technology scaling increases clock rates and die sizes; therefore, power dissipation is predicted to soon become the key limiting factor on the performance of…”
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