Search Results - "2007 44th ACM/IEEE Design Automation Conference"

The impact of NBTI on the performance of combinational and sequential circuits by Wang, Wenping, Yang, Shengqi, Bhardwaj, Sarvesh, Vattikonda, Rakesh, Vrudhula, Sarma, Liu, Frank, Cao, Yu

“…Negative-bias-temperature-instability (NBTI) has become the primary limiting factor of circuit lifetime. In this work, we develop a general framework for…”
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Formal Techniques for SystemC Verification; Position Paper by Vardi, M.Y.

“…SystemC has emerged lately as a de facto, open, industry standard modeling language, enabling a wide range of modeling levels, from RTL to system level. Its…”
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Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors by Puttaswamy, K., Loh, G.H.

“…Three-dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked…”
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Design-Silicon Timing Correlation A Data Mining Perspective by Wang, L.-C., Bastani, P., Abadir, M.S.

“…In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitors and (2) delay testing. In the past, delay test data has…”
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Optimization of Area in Digital FIR Filters using Gate-Level Metrics by Aksoy, L., Costa, E., Flores, P., Monteiro, J.

“…In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its…”
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Thousand Core ChipsA Technology Perspective by Borkar, S.

“…This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power…”
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Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures by Banerjee, S., Bozorgzadeh, E., Noguera, J., Dutt, N.

“…Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources…”
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A. Richard Newton, 1951 - 2007 by Levitan, S.P.

“…Summary form only given, as follows. Richard was also a strong supporter of the Design Automation Conference (DAC); he was the Chair of the conference in 1991,…”
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FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs by do Carmo Lucas, A., Heithecker, S., Ernst, R.

“…Digital film processing is characterized by a resolution of at least 2 K (2048times1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2…”
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Functional Verification of SiCortex Multiprocessor System-on-a-Chip by Petlin, O., Snyder, W.

“…This paper discusses functional verification of the SiCortex multiprocessor compute node. It is shown that the implementation of reusable verification…”
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IP Exchange: I'll Show You Mine if You Show Me Yours by Sarno, Lauren, Wilson, Ron, Eo, Soo-Kwan, Lestringand, Laurent, Goodenough, John, Stark, Guri, Leef, Serge, Witt, Dave

“…Between concept and production, there are many points where hardware and software developers need to exchange requirements and intellectual property. What data…”
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Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch by Kim, Jaeha, Jones, Kevin D., Horowitz, Mark A.

“…This paper describes a noise-based method of estimating the effects of device random mismatch on circuit's transient response, such as delay and frequency. The…”
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Marie R. Pistilli Women in EDA Achievement Award

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Parameterized macromodeling for analog system-level design exploration by Wang, Jian, Li, Xin, Pileggi, Lawrence T.

“…In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small…”
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Early Power-Aware Design & Validation: Myth or Reality? by Kamhi, Gila, Miller, Sarah, Mentor, Stephen Bailey, Nebel, Wolfgang H., Wong, YC, Karmann, Juergen, Macii, Enrico, Kosonocky, Stephen, Curtis, Steve

“…Design for low power is crucial for developing and optimizing complex SoCs. Typically, power issues are tackled at the gate-level and backend stages,…”
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Modeling and analysis of non-rectangular gate for post-lithography circuit simulation by Singhal, Ritu, Balijepalli, Asha, Subramaniam, Anupama, Liu, Frank, Nassif, Sani, Cao, Yu

“…In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography…”
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CAD-based security, cryptography, and digital rights management by Koushanfar, Farinaz, Potkonjak, Miodrag

“…Manufacturing variability is inherent to many silicon and nano-scale technologies and can be manifested in many different ways and modalities (e.g. power and…”
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Non-linear statistical static timing analysis for non-Gaussian variation sources by Cheng, Lerong, Xiong, Jinjun, He, Lei

“…Existing statistical static timing analysis (SSTA) techniques suffer from limited modeling capability by using a linear delay model with Gaussian distribution,…”
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Synthesizing SVA local variables for formal verification by Long, Jiang, Seawright, Andrew

“…This paper describes techniques for efficiently handling a subset of System Verilog Assertion(SVA) safety properties with local variables in formal…”
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Modeling and estimation of full-chip leakage current considering within-die correlation by Heloue, Khaled R., Azizi, Navid, Najm, Farid N.

“…We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both…”
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