Search Results - "2006 European Solid-State Device Research Conference"

Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric by Boucart, K., Ionescu, A.M.

“…In this paper we propose a novel design for a double gate tunnel field effect transistor (DG TFET), for which the simulations show significant improvements…”
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Highly Reliable TiN/ZrO2/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies by Berthelot, A., Caillat, C., Huard, V., Barnola, S., Boeck, B., Del-Puppo, H., Emonet, N., Lalanne, F.

“…For the first time, we report a complete evaluation of a TiN/ZrO 2 /TiN stacked capacitor suitable for 45 nm embedded DRAM (eDRAM). Indeed, this study, done on…”
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Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs by Gnani, E., Reggiani, S., Rudan, M., Baccarani, G.

“…In this work we investigate the performance of fully-depleted silicon-on-insulator (SOI), double-gate (DG) and cylindrical nanowire (CNW) FETs, with the aim of…”
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Impact of Random Dopant Fluctuation on Bulk CMOS 6-T SRAM Scaling by Cheng, B., Roy, S., Roy, G., Brown, A., Asenov, A.

“…Based on the statistical 3D device simulation of well scaled 25, 18 and 13nm physical gate length bulk MOSFETs, the impact of random dopant fluctuation on 6-T…”
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New TIT Capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60nm and below DRAMs by Ho Jin Cho, Young Dae Kim, Dong Su Park, Euna Lee, Cheol Hwan Park, Jun Soo Jang, Keum Bum Lee, Hai Won Kim, Soo Jin Chae, Young Jong Ki, Il Keun Han, Yong Wook Song

“…New ZrO 2 /Al 2 O 3 /ZrO 2 (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60nm and below technologies. ZAZ dielectric film…”
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Al2O3 Based Flash Interpoly Dielectrics: a Comparative Retention Study by Wellekens, D., Blomme, P., Govoreanu, B., De Vos, J., Haspeslagh, L., Van Houdt, J., Brunco, D.P., van der Zanden, K.

“…In this work the authors present a thorough investigation of charge retention in memory cells with SiO 2 /Al 2 O 3 interpoly dielectric (IPD) stacks, using a…”
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Fixed-Pattern Noise Induced by Transmission Gate in Pinned 4T CMOS Image Sensor Pixels by Xinyang Wang, Rao, P.R., Theuwissen, A.J.P.

“…In this paper, we present the characterization and analysis of fixed-pattern noise (FPN) in CMOS image sensor (CIS) pixels fabricated in CMOS 0.18-mum process…”
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Foreword

“…Presents the welcome message from the conference proceedings…”
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Integrated Micromechanical Circuits for RF Front Ends by Nguyen, C.T.C.

“…Having now produced devices with sufficient Q, thermal stability, aging stability, and manufacturability, vibrating RF MEMS technology is already finding its…”
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Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell by Rajiv Joshi, Rouwaida Kanj, Nassif, S., Plass, D., Yuen Chan, Ching-Te Chuang

“…This paper describes the application of a novel variability-driven statistical analysis methodology to study the stability/performance of SRAM designs in 65nm…”
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Self Heating Simulation of Multi-Gate FETs by Molzer, W., Schulz, T., Xiong, W., Cleavelin, R.C., Schrufer, K., Marshall, A., Matthews, K., Sedlmeir, J., Siprak, D., Knoblinger, G., Bertolissi, L., Patruno, P., Colinge, J.-P.

“…Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled…”
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Schottky Tunneling Source MOSFET Design for Mixed Mode and Analog Applications by Jhaveri, R., Woo, J.

“…A novel asymmetric Schottky tunneling source MOSFET is proposed in this paper. The main feature of this device is the concept of gate controlled Schottky…”
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Local volume inversion and corner effects in triangular gate-all-around MOSFETs by Moselund, K.B., Bouvet, D., Tschuor, L., Pott, V., Dainesi, P., Ionescu, A.M.

“…We report on the fabrication and measurement of triangular gate-all-around (GAA) and tri-gate devices. On the small triangular cross-section devices we observe…”
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Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study by Brown, A.R., Roy, G., Asenov, A.

“…In this paper we present a 3D simulation study of the effect of Fermi level pinning along polysilicon gate grain boundaries on nano-MOSFET variability. Pinning…”
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Co-integration of 2 mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS by Mayer, F., Le Royer, C., Le Carval, G., Tabone, C., Clavelier, L., Deleonibus, S.

“…The reduction of the subthreshold slope S in conventional MOSFETs hits against the diffusion phenomena which limits S to 60 mV/dec at 300K. This paper deals…”
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Assessment of the Impact of Biaxial Strain on the Drain Current of Decanometric n-MOSFET by Ponton, D., Lucci, L., Palestri, P., Esseni, D., Selmi, L.

“…In this paper, the authors use multi-subband-Monte-Carlo simulations to investigate the on-current increment induced by biaxial strain in n-MOSFETs featuring…”
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FinFET: the prospective multi-gate device for future SoC applications by Inaba, S., Okano, K., Izumida, T., Kaneko, A., Kawasaki, H., Yagishita, A., Kanemura, T., Ishida, T., Aoki, N., Ishimaru, K., Suguro, K., Eguchi, K., Tsunashima, Y., Toyoshima, Y., Ishiuchi, H.

“…This paper discusses the possibility of future large scale integration (LSI) of multi-gate device. FinFET is thought to be the most promising multi-gate device…”
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Scaling aspects of microjoints for 3D chip interconnects by Munding, A., Kaiser, A., Benkart, P., Kohn, E., Heittmann, A., Hiibner, H., Ramacher, U.

“…Scaling of microjoints in 3-dimensional chip stacks is proposed by means of kinetic control. Therefore, phase growth in the copper/tin system in presence of…”
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LASER Anneal to Enable Ultimate CMOS Scaling with PMOS Band Edge Metal Gate/High-K Stacks by Gilmer, D.C., Schaeffer, J.K., Taylor, W.J., Spencer, G., Triyoso, D.H., Raymond, M., Roan, D., Smith, J., Capasso, C., Hegde, R.I., Samavedam, S.B.

“…For the first time, we report on the beneficial result for minimizing the activation thermal budget using LASER anneals with metal-oxide-gate-electrode/high-k…”
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Reliability Comparison of Al2O3 and HfSiON for use as Interpoly Dielectric in Flash Arrays by Miranda, A.H., van Schaijk, R., van Duuren, M., Akil, N., Golubovic, D.S.

“…For the scaling of embedded floating gate (FG) memories towards the 45nm CMOS generation and beyond, a reduction of the program and erase voltages is required…”
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