Search Results - "2006 Electrical Overstress/Electrostatic Discharge Symposium"

ESD protection considerations in advanced high-voltage technologies for automotive by Mergens, M.P.J., Mayerhofer, M.T., Willemen, J.A., Stecher, M.

“…This paper discusses challenges and solutions of automotive ESD protection design in a reliability driven industry. Various ESD/EMI specifications are…”
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Ultra-thin gate oxide reliability in the ESD time domain by Ille, A., Stadler, W., Kerber, A., Pompl, T., Brodbeck, T., Esmark, K., Bravaix, A.

“…The universality of the power-law model for the time to breakdown of thin gate oxides is experimentally established from ldquoDCrdquo down to the ESD regime…”
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Characterization and modeling of three CMOS diode structures in the CDM to HBM timeframe by Stockinger, M., Miller, J.W.

“…We present advanced TLP measurement techniques down to 1.2ns pulses. We compare gated, STI and abutted tie diodes and introduce a compact model with a new…”
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Cable discharges into communication interfaces by Stadler, W., Brodbeck, T., Gartner, R., Gossner, H.

“…Current amplitudes of a cable discharge event (CDE) are a risk for electronic interfaces if a cable can discharge directly into a signal pin. CDE have been…”
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ESD protection for high-voltage CMOS technologies by Quittard, O., Mrcarica, Z., Blanc, F., Notermans, G., Smedes, T., van Zwol, H.

“…Two types of ESD protection for high-voltage CMOS technologies are presented. Both solutions can be readily ported between different HV CMOS process options…”
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Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection by Junjun Li, Gauthier, R., Mitra, S., Putnam, C., Chatty, K., Halbach, R., Seguin, C.

“…We present a novel multi-RC-triggered MOSFET-based power clamp with up to 70% trigger circuit area reduction and improved transient HBM, MM, and CDM ESD…”
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System level stress and the impact on device ESD protection by Stadler, Wolfgang

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Cleanrooms/ESD/lonization guidelines and considerations by Long, Christopher

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ESD troubleshooting and testing practices by Kunz, Hans

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ESD protection considerations in high voltage technologies by Mergens, Markus

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Layout for ESD and latchup robustness by Righter, Alan

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Controlling ESD in automated process equipment by Bellmore, Donn

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ESD control and design for extremely sensitive ("Class 0") devices by Perry, Robert

“…Summary form only given, as follows. Due to cost and other considerations, the ESDA believes that more and more devices, including common integrated circuits,…”
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Automated ESD rule verification & EDA tools by Gossner, Harald

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Relations between system level ESD and (vf-)TLP by Smedes, T., van Zwol, J., de Raad, G., Brodbeck, T., Wolf, H.

“…This paper shows that device robustness for system level ESD scales linearly with device width. Relations between system level failure voltages and TLP failure…”
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Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced Smart Power technology by Gendron, A., Salamero, C., Bafleur, M., Nolhier, N., Renaud, P., Besse, P.

“…A new approach, based on reduced and no-snapback components, was studied to face high-voltages I/Os severe ESD specifications. An accurate physical analysis of…”
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Outstanding contribution award

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Advanced topics in ESD auditing

“…Summary form only given, as follows. A record of the workshop was not made available for publication as part of the conference proceedings. This workshop will…”
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A.2 CDM at the nanoscale frontier

“…Summary form only given, as follows. A record of the workshop was not made available for publication as part of the conference proceedings. This workshop will…”
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General Chair's Welcome

“…Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the…”
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