Search Results - "2002 Electrical Overstress/Electrostatic Discharge Symposium"

High frequency instabilities in GMR heads due to metal-to-metal contact ESD transients by Patland, Henry, Ogle, Wade A.

“…Utilizing a D-CDM (Direct Charged Device Model) ESD tester this study evaluates the failure rates of GMR heads by measuring high frequency instability noise…”
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A novel on-chip ESD protection circuit for GaAs HBT RF power amplifiers by Ma, Yintat, Li, G. P.

“…A low capacitance, on-chip Electrostatic Discharge (ESD) protection circuit for GaAs power amplifiers that does not degrade RF circuit performance is…”
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A study of high current characteristics of devices in a 0.13µm CMOS technology by Tan, Pee-Ya, Manna, Indrajit, Tan, Yew-Chee, Lo, Keng-Foo, Li, Pian-Hong

“…This paper evaluates the high current performance of several devices in 0.13µm CMOS process as function of layout parameters using transmission line pulse…”
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The impact of substrate resistivity on ESD protection devices by Smedes, T., Heringa, A., van Zwol, J., de Jong, P.C.

“…The substrate resistivity has a serious impact on the behaviour of ESD protection devices. TLP characterisation and failure analysis show that different…”
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Variable-trigger voltage ESD Power Clamps for mixed voltage applications using a 120 GHz/100 GHz (fT/fMAX) Silicon Germanium Heterojunction Bipolar Transistor with Carbon incorporation by Voldman, Steven H.

“…A novel ESD Power Clamps for 40 GHz applications, using a 120 GHz/100 GHz f T /f MAX Silicon Germanium Heterojunction Bipolar Transistor (HBT) with Carbon…”
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Sources of impulsive EMI in large server farms by Smith, Douglas C., Henry, Leo G., Hogsett, Mark, Nuebel, Joe

“…Further research is reported on EMI in large server installations.[1] Data is presented from both staged events and server environments. The data confirms the…”
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ESD damage by arcing near GMR heads by Teng, Zhao-Yu, Wang, You-Gui, Li, William, Tao, Rock

“…This paper reports the ESD damage of GMR heads in gold ball bonding process (GBB), which utilizes a high voltage arc to form a gold ball, then ultrasonically…”
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Effects of ESD transients on the properties of GMR heads by Granstrom, Eric, Cho, Haeseok, Stokes, Scott, Srun, Seakly, Tabat, Ned

“…Simulated ESD transients with pulsewidths from 0.1 nsec to 10 nsec were applied to GMR heads. From 1 to 10 nsec essentially no changes in failure voltages are…”
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Copper interconnect microanalysis and electromigration reliability performance due to the impact of TLP ESD by Sherry, Suat Cheng Khoo, Tan, P-Y, Chua, E-C, Tan Carol, S-C, Manna, I., Redkar, S., Ansari, S.

“…Electrostatic discharge events can degrade the electromigration (EM) reliability of devices. Transmission Line Pulsing (TLP) is used to simulate such an…”
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New considerations for MOSFET power clamps by Poon, Steven S., Maloney, Timothy J.

“…Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in…”
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Magnetoresistive Sensitivity Mapping (MSM) and dynamic electrical test (DET) correlation study on GMR sensor induced by low threshold ESD stress by Hung, S. T., Bordeos, R., Zhang, L. Z., Wong, C.Y.

“…In the case of soft ESD damage, the GMR read sensor was magnetically changed caused by ESD stress. With magnetoresistive sens itivity mapping (MSM), which is…”
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Modelling and extraction of RF performance parameters of CMOS Electrostatic Discharge protection devices by Vassilev, V., Groeseneken, G., Jenei, S., Venegas, R., Steyaert, M., Maes, H.

“…The HF parasitic behaviour of two terminal, CMOS Electrostatic Discharge (ESD) protection devices is studied. Basic small signal RC equivalent models and…”
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Optimization of input protection diode for high speed applications by Worley, Eugene R., Bakulin, Alex

“…Optimization of input protection diodes for high-speed applications including RF and Internet receivers is examined. The key parameters used to rate the diodes…”
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New ESD protection circuits based on PNP triggering SCR for advanced CMOS device applications by Morishita, Yasuyuki

“…New silicon controlled rectifier (SCR) structures for ESD protection circuits, with low parasitic capacitance, are proposed. These new SCR structures are…”
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An automated electrostatic discharge computer-aided design system with the incorporation of hierarchical parameterized cells in BiCMOS analog and RF technology for mixed signal applications by Voldman, Steven H., Strang, Susan E., Jordan, Donald

“…Development of an automated ESD design system for analog and Radio Frequency (RF) technologies using a hierarchy of RF-characterized higher order graphical…”
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A 6mW, 1.5dB NF CMOS LNA for GPS with 3kV HBM ESD-protection by Leroux, Paul, Vassilev, Vesselin, Steyaert, Michiel, Maes, Herman

“…This paper describes the design of a high performance 0.25µm CMOS Low Noise Amplifier (LNA) for the Global Positioning System (GPS) operating at 1.57GHz. The…”
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ESD in magnetic recording by Goceman, Ferruh

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Investigation for a Smart Power and self-protected device under ESD stress through geometry and design considerations for automotive applications by Besse, Patrice, Nolhier, Nicolas, Bafleur, Marise, Zecri, Michel, Chung, Young

“…This paper deals with a detailed study of the ESD capability of self-protected LDMOS used for automotive applications. Failure mechanisms of LDMOS devices…”
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High Holding Current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation by Mergens, Markus P.J., Russ, Christian C., Verhaege, Koen G., Armer, John, Jozwiak, Phillip C., Mohn, Russ

“…This paper presents a novel SCR for power line and local I/O ESD protection. The HHI-SCR exhibits a dual ESD clamp characteristic: low-current high-voltage…”
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Technology CAD evaluation of BiCMOS protection structures operation including spatial thermal runaway by Vashchenko, Vladislav, Concannon, Ann, Ter Beek, Marcel, Hopper, Peter

“…A 2-D simulation approach that takes into account the 3D effects of electro-thermal instability during ESD operation, is presented. The method is used to…”
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